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Searched refs:tlbix (Results 1 – 25 of 63) sorted by relevance

123

/dports/emulators/hercules/hercules-3.13/
H A Ddat.h848 && (regs->tlb.common[tlbix] || regs->dat.asd == regs->tlb.TLB_ASD(tlbix)) in ARCH_DEP()
852 pte = regs->tlb.TLB_PTE(tlbix); in ARCH_DEP()
856 if (regs->tlb.protect[tlbix]) in ARCH_DEP()
956 regs->tlb.TLB_ASD(tlbix^1) = regs->tlb.TLB_ASD(tlbix); in ARCH_DEP()
958 regs->tlb.TLB_PTE(tlbix^1) = regs->tlb.TLB_PTE(tlbix); in ARCH_DEP()
959 regs->tlb.common[tlbix^1] = regs->tlb.common[tlbix]; in ARCH_DEP()
960 regs->tlb.protect[tlbix^1] = regs->tlb.protect[tlbix]; in ARCH_DEP()
1003 && (regs->tlb.common[tlbix] || regs->dat.asd == regs->tlb.TLB_ASD(tlbix)) in ARCH_DEP()
1008 if (regs->tlb.protect[tlbix]) in ARCH_DEP()
1136 && (regs->tlb.common[tlbix] || regs->dat.asd == regs->tlb.TLB_ASD(tlbix)) in ARCH_DEP()
[all …]
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/mips/mach-mscc/
H A Dcpu.c39 register int tlbix = 0; in vcoreiii_tlb_init() local
49 create_tlb(tlbix++, MSCC_IO_ORIGIN1_OFFSET, SZ_16M, MMU_REGIO_RW, in vcoreiii_tlb_init()
52 create_tlb(tlbix++, MSCC_IO_ORIGIN2_OFFSET, SZ_16M, MMU_REGIO_RW, in vcoreiii_tlb_init()
61 create_tlb(tlbix++, MSCC_FLASH_TO, SZ_16M, MMU_REGIO_RO_C, in vcoreiii_tlb_init()
63 create_tlb(tlbix++, MSCC_FLASH_TO + SZ_32M, SZ_16M, MMU_REGIO_RO_C, in vcoreiii_tlb_init()
71 create_tlb(tlbix++, MSCC_DDR_TO, MSCC_RAM_TLB_SIZE, MMU_REGIO_RW, in vcoreiii_tlb_init()
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/mips/mach-mscc/
H A Dcpu.c39 register int tlbix = 0; in vcoreiii_tlb_init() local
49 create_tlb(tlbix++, MSCC_IO_ORIGIN1_OFFSET, SZ_16M, MMU_REGIO_RW, in vcoreiii_tlb_init()
52 create_tlb(tlbix++, MSCC_IO_ORIGIN2_OFFSET, SZ_16M, MMU_REGIO_RW, in vcoreiii_tlb_init()
61 create_tlb(tlbix++, MSCC_FLASH_TO, SZ_16M, MMU_REGIO_RO_C, in vcoreiii_tlb_init()
63 create_tlb(tlbix++, MSCC_FLASH_TO + SZ_32M, SZ_16M, MMU_REGIO_RO_C, in vcoreiii_tlb_init()
71 create_tlb(tlbix++, MSCC_DDR_TO, MSCC_RAM_TLB_SIZE, MMU_REGIO_RW, in vcoreiii_tlb_init()
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/mips/mach-mscc/
H A Dcpu.c39 register int tlbix = 0; in vcoreiii_tlb_init() local
49 create_tlb(tlbix++, MSCC_IO_ORIGIN1_OFFSET, SZ_16M, MMU_REGIO_RW, in vcoreiii_tlb_init()
52 create_tlb(tlbix++, MSCC_IO_ORIGIN2_OFFSET, SZ_16M, MMU_REGIO_RW, in vcoreiii_tlb_init()
61 create_tlb(tlbix++, MSCC_FLASH_TO, SZ_16M, MMU_REGIO_RO_C, in vcoreiii_tlb_init()
63 create_tlb(tlbix++, MSCC_FLASH_TO + SZ_32M, SZ_16M, MMU_REGIO_RO_C, in vcoreiii_tlb_init()
71 create_tlb(tlbix++, MSCC_DDR_TO, MSCC_RAM_TLB_SIZE, MMU_REGIO_RW, in vcoreiii_tlb_init()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/mips/mach-mscc/
H A Dcpu.c39 register int tlbix = 0; in vcoreiii_tlb_init() local
49 create_tlb(tlbix++, MSCC_IO_ORIGIN1_OFFSET, SZ_16M, MMU_REGIO_RW, in vcoreiii_tlb_init()
52 create_tlb(tlbix++, MSCC_IO_ORIGIN2_OFFSET, SZ_16M, MMU_REGIO_RW, in vcoreiii_tlb_init()
61 create_tlb(tlbix++, MSCC_FLASH_TO, SZ_16M, MMU_REGIO_RO_C, in vcoreiii_tlb_init()
63 create_tlb(tlbix++, MSCC_FLASH_TO + SZ_32M, SZ_16M, MMU_REGIO_RO_C, in vcoreiii_tlb_init()
71 create_tlb(tlbix++, MSCC_DDR_TO, MSCC_RAM_TLB_SIZE, MMU_REGIO_RW, in vcoreiii_tlb_init()
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/arch/mips/mach-mscc/
H A Dcpu.c39 register int tlbix = 0; in vcoreiii_tlb_init() local
49 create_tlb(tlbix++, MSCC_IO_ORIGIN1_OFFSET, SZ_16M, MMU_REGIO_RW, in vcoreiii_tlb_init()
52 create_tlb(tlbix++, MSCC_IO_ORIGIN2_OFFSET, SZ_16M, MMU_REGIO_RW, in vcoreiii_tlb_init()
61 create_tlb(tlbix++, MSCC_FLASH_TO, SZ_16M, MMU_REGIO_RO_C, in vcoreiii_tlb_init()
63 create_tlb(tlbix++, MSCC_FLASH_TO + SZ_32M, SZ_16M, MMU_REGIO_RO_C, in vcoreiii_tlb_init()
71 create_tlb(tlbix++, MSCC_DDR_TO, MSCC_RAM_TLB_SIZE, MMU_REGIO_RW, in vcoreiii_tlb_init()
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/mips/mach-mscc/
H A Dcpu.c43 register int tlbix = 0; in vcoreiii_tlb_init() local
53 create_tlb(tlbix++, MSCC_IO_ORIGIN1_OFFSET, SZ_16M, MMU_REGIO_RW, in vcoreiii_tlb_init()
56 create_tlb(tlbix++, MSCC_IO_ORIGIN2_OFFSET, SZ_16M, MMU_REGIO_RW, in vcoreiii_tlb_init()
64 create_tlb(tlbix++, MSCC_FLASH_TO, SZ_16M, MMU_REGIO_RO_C, in vcoreiii_tlb_init()
66 create_tlb(tlbix++, MSCC_FLASH_TO + SZ_32M, SZ_16M, MMU_REGIO_RO_C, in vcoreiii_tlb_init()
74 create_tlb(tlbix++, MSCC_DDR_TO, MSCC_RAM_TLB_SIZE, MMU_REGIO_RW, in vcoreiii_tlb_init()
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/mips/mach-mscc/
H A Dcpu.c43 register int tlbix = 0; in vcoreiii_tlb_init() local
53 create_tlb(tlbix++, MSCC_IO_ORIGIN1_OFFSET, SZ_16M, MMU_REGIO_RW, in vcoreiii_tlb_init()
56 create_tlb(tlbix++, MSCC_IO_ORIGIN2_OFFSET, SZ_16M, MMU_REGIO_RW, in vcoreiii_tlb_init()
64 create_tlb(tlbix++, MSCC_FLASH_TO, SZ_16M, MMU_REGIO_RO_C, in vcoreiii_tlb_init()
66 create_tlb(tlbix++, MSCC_FLASH_TO + SZ_32M, SZ_16M, MMU_REGIO_RO_C, in vcoreiii_tlb_init()
74 create_tlb(tlbix++, MSCC_DDR_TO, MSCC_RAM_TLB_SIZE, MMU_REGIO_RW, in vcoreiii_tlb_init()
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/mips/mach-mscc/
H A Dcpu.c43 register int tlbix = 0; in vcoreiii_tlb_init() local
53 create_tlb(tlbix++, MSCC_IO_ORIGIN1_OFFSET, SZ_16M, MMU_REGIO_RW, in vcoreiii_tlb_init()
56 create_tlb(tlbix++, MSCC_IO_ORIGIN2_OFFSET, SZ_16M, MMU_REGIO_RW, in vcoreiii_tlb_init()
64 create_tlb(tlbix++, MSCC_FLASH_TO, SZ_16M, MMU_REGIO_RO_C, in vcoreiii_tlb_init()
66 create_tlb(tlbix++, MSCC_FLASH_TO + SZ_32M, SZ_16M, MMU_REGIO_RO_C, in vcoreiii_tlb_init()
74 create_tlb(tlbix++, MSCC_DDR_TO, MSCC_RAM_TLB_SIZE, MMU_REGIO_RW, in vcoreiii_tlb_init()
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/mips/mach-mscc/
H A Dcpu.c43 register int tlbix = 0; in vcoreiii_tlb_init() local
53 create_tlb(tlbix++, MSCC_IO_ORIGIN1_OFFSET, SZ_16M, MMU_REGIO_RW, in vcoreiii_tlb_init()
56 create_tlb(tlbix++, MSCC_IO_ORIGIN2_OFFSET, SZ_16M, MMU_REGIO_RW, in vcoreiii_tlb_init()
64 create_tlb(tlbix++, MSCC_FLASH_TO, SZ_16M, MMU_REGIO_RO_C, in vcoreiii_tlb_init()
66 create_tlb(tlbix++, MSCC_FLASH_TO + SZ_32M, SZ_16M, MMU_REGIO_RO_C, in vcoreiii_tlb_init()
74 create_tlb(tlbix++, MSCC_DDR_TO, MSCC_RAM_TLB_SIZE, MMU_REGIO_RW, in vcoreiii_tlb_init()
/dports/sysutils/u-boot-chip/u-boot-2021.07/arch/mips/mach-mscc/
H A Dcpu.c43 register int tlbix = 0; in vcoreiii_tlb_init() local
53 create_tlb(tlbix++, MSCC_IO_ORIGIN1_OFFSET, SZ_16M, MMU_REGIO_RW, in vcoreiii_tlb_init()
56 create_tlb(tlbix++, MSCC_IO_ORIGIN2_OFFSET, SZ_16M, MMU_REGIO_RW, in vcoreiii_tlb_init()
64 create_tlb(tlbix++, MSCC_FLASH_TO, SZ_16M, MMU_REGIO_RO_C, in vcoreiii_tlb_init()
66 create_tlb(tlbix++, MSCC_FLASH_TO + SZ_32M, SZ_16M, MMU_REGIO_RO_C, in vcoreiii_tlb_init()
74 create_tlb(tlbix++, MSCC_DDR_TO, MSCC_RAM_TLB_SIZE, MMU_REGIO_RW, in vcoreiii_tlb_init()
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/mips/mach-mscc/
H A Dcpu.c43 register int tlbix = 0; in vcoreiii_tlb_init() local
53 create_tlb(tlbix++, MSCC_IO_ORIGIN1_OFFSET, SZ_16M, MMU_REGIO_RW, in vcoreiii_tlb_init()
56 create_tlb(tlbix++, MSCC_IO_ORIGIN2_OFFSET, SZ_16M, MMU_REGIO_RW, in vcoreiii_tlb_init()
64 create_tlb(tlbix++, MSCC_FLASH_TO, SZ_16M, MMU_REGIO_RO_C, in vcoreiii_tlb_init()
66 create_tlb(tlbix++, MSCC_FLASH_TO + SZ_32M, SZ_16M, MMU_REGIO_RO_C, in vcoreiii_tlb_init()
74 create_tlb(tlbix++, MSCC_DDR_TO, MSCC_RAM_TLB_SIZE, MMU_REGIO_RW, in vcoreiii_tlb_init()
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/mips/mach-mscc/
H A Dcpu.c43 register int tlbix = 0; in vcoreiii_tlb_init() local
53 create_tlb(tlbix++, MSCC_IO_ORIGIN1_OFFSET, SZ_16M, MMU_REGIO_RW, in vcoreiii_tlb_init()
56 create_tlb(tlbix++, MSCC_IO_ORIGIN2_OFFSET, SZ_16M, MMU_REGIO_RW, in vcoreiii_tlb_init()
64 create_tlb(tlbix++, MSCC_FLASH_TO, SZ_16M, MMU_REGIO_RO_C, in vcoreiii_tlb_init()
66 create_tlb(tlbix++, MSCC_FLASH_TO + SZ_32M, SZ_16M, MMU_REGIO_RO_C, in vcoreiii_tlb_init()
74 create_tlb(tlbix++, MSCC_DDR_TO, MSCC_RAM_TLB_SIZE, MMU_REGIO_RW, in vcoreiii_tlb_init()
/dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/mips/mach-mscc/
H A Dcpu.c43 register int tlbix = 0; in vcoreiii_tlb_init() local
53 create_tlb(tlbix++, MSCC_IO_ORIGIN1_OFFSET, SZ_16M, MMU_REGIO_RW, in vcoreiii_tlb_init()
56 create_tlb(tlbix++, MSCC_IO_ORIGIN2_OFFSET, SZ_16M, MMU_REGIO_RW, in vcoreiii_tlb_init()
64 create_tlb(tlbix++, MSCC_FLASH_TO, SZ_16M, MMU_REGIO_RO_C, in vcoreiii_tlb_init()
66 create_tlb(tlbix++, MSCC_FLASH_TO + SZ_32M, SZ_16M, MMU_REGIO_RO_C, in vcoreiii_tlb_init()
74 create_tlb(tlbix++, MSCC_DDR_TO, MSCC_RAM_TLB_SIZE, MMU_REGIO_RW, in vcoreiii_tlb_init()
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/mips/mach-mscc/
H A Dcpu.c43 register int tlbix = 0; in vcoreiii_tlb_init() local
53 create_tlb(tlbix++, MSCC_IO_ORIGIN1_OFFSET, SZ_16M, MMU_REGIO_RW, in vcoreiii_tlb_init()
56 create_tlb(tlbix++, MSCC_IO_ORIGIN2_OFFSET, SZ_16M, MMU_REGIO_RW, in vcoreiii_tlb_init()
64 create_tlb(tlbix++, MSCC_FLASH_TO, SZ_16M, MMU_REGIO_RO_C, in vcoreiii_tlb_init()
66 create_tlb(tlbix++, MSCC_FLASH_TO + SZ_32M, SZ_16M, MMU_REGIO_RO_C, in vcoreiii_tlb_init()
74 create_tlb(tlbix++, MSCC_DDR_TO, MSCC_RAM_TLB_SIZE, MMU_REGIO_RW, in vcoreiii_tlb_init()
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/mips/mach-mscc/
H A Dcpu.c43 register int tlbix = 0; in vcoreiii_tlb_init() local
53 create_tlb(tlbix++, MSCC_IO_ORIGIN1_OFFSET, SZ_16M, MMU_REGIO_RW, in vcoreiii_tlb_init()
56 create_tlb(tlbix++, MSCC_IO_ORIGIN2_OFFSET, SZ_16M, MMU_REGIO_RW, in vcoreiii_tlb_init()
64 create_tlb(tlbix++, MSCC_FLASH_TO, SZ_16M, MMU_REGIO_RO_C, in vcoreiii_tlb_init()
66 create_tlb(tlbix++, MSCC_FLASH_TO + SZ_32M, SZ_16M, MMU_REGIO_RO_C, in vcoreiii_tlb_init()
74 create_tlb(tlbix++, MSCC_DDR_TO, MSCC_RAM_TLB_SIZE, MMU_REGIO_RW, in vcoreiii_tlb_init()
/dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/mips/mach-mscc/
H A Dcpu.c43 register int tlbix = 0; in vcoreiii_tlb_init() local
53 create_tlb(tlbix++, MSCC_IO_ORIGIN1_OFFSET, SZ_16M, MMU_REGIO_RW, in vcoreiii_tlb_init()
56 create_tlb(tlbix++, MSCC_IO_ORIGIN2_OFFSET, SZ_16M, MMU_REGIO_RW, in vcoreiii_tlb_init()
64 create_tlb(tlbix++, MSCC_FLASH_TO, SZ_16M, MMU_REGIO_RO_C, in vcoreiii_tlb_init()
66 create_tlb(tlbix++, MSCC_FLASH_TO + SZ_32M, SZ_16M, MMU_REGIO_RO_C, in vcoreiii_tlb_init()
74 create_tlb(tlbix++, MSCC_DDR_TO, MSCC_RAM_TLB_SIZE, MMU_REGIO_RW, in vcoreiii_tlb_init()
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/mips/mach-mscc/
H A Dcpu.c43 register int tlbix = 0; in vcoreiii_tlb_init() local
53 create_tlb(tlbix++, MSCC_IO_ORIGIN1_OFFSET, SZ_16M, MMU_REGIO_RW, in vcoreiii_tlb_init()
56 create_tlb(tlbix++, MSCC_IO_ORIGIN2_OFFSET, SZ_16M, MMU_REGIO_RW, in vcoreiii_tlb_init()
64 create_tlb(tlbix++, MSCC_FLASH_TO, SZ_16M, MMU_REGIO_RO_C, in vcoreiii_tlb_init()
66 create_tlb(tlbix++, MSCC_FLASH_TO + SZ_32M, SZ_16M, MMU_REGIO_RO_C, in vcoreiii_tlb_init()
74 create_tlb(tlbix++, MSCC_DDR_TO, MSCC_RAM_TLB_SIZE, MMU_REGIO_RW, in vcoreiii_tlb_init()
/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/mips/mach-mscc/
H A Dcpu.c43 register int tlbix = 0; in vcoreiii_tlb_init() local
53 create_tlb(tlbix++, MSCC_IO_ORIGIN1_OFFSET, SZ_16M, MMU_REGIO_RW, in vcoreiii_tlb_init()
56 create_tlb(tlbix++, MSCC_IO_ORIGIN2_OFFSET, SZ_16M, MMU_REGIO_RW, in vcoreiii_tlb_init()
64 create_tlb(tlbix++, MSCC_FLASH_TO, SZ_16M, MMU_REGIO_RO_C, in vcoreiii_tlb_init()
66 create_tlb(tlbix++, MSCC_FLASH_TO + SZ_32M, SZ_16M, MMU_REGIO_RO_C, in vcoreiii_tlb_init()
74 create_tlb(tlbix++, MSCC_DDR_TO, MSCC_RAM_TLB_SIZE, MMU_REGIO_RW, in vcoreiii_tlb_init()
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/mips/mach-mscc/
H A Dcpu.c43 register int tlbix = 0; in vcoreiii_tlb_init() local
53 create_tlb(tlbix++, MSCC_IO_ORIGIN1_OFFSET, SZ_16M, MMU_REGIO_RW, in vcoreiii_tlb_init()
56 create_tlb(tlbix++, MSCC_IO_ORIGIN2_OFFSET, SZ_16M, MMU_REGIO_RW, in vcoreiii_tlb_init()
64 create_tlb(tlbix++, MSCC_FLASH_TO, SZ_16M, MMU_REGIO_RO_C, in vcoreiii_tlb_init()
66 create_tlb(tlbix++, MSCC_FLASH_TO + SZ_32M, SZ_16M, MMU_REGIO_RO_C, in vcoreiii_tlb_init()
74 create_tlb(tlbix++, MSCC_DDR_TO, MSCC_RAM_TLB_SIZE, MMU_REGIO_RW, in vcoreiii_tlb_init()
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/mips/mach-mscc/
H A Dcpu.c43 register int tlbix = 0; in vcoreiii_tlb_init() local
53 create_tlb(tlbix++, MSCC_IO_ORIGIN1_OFFSET, SZ_16M, MMU_REGIO_RW, in vcoreiii_tlb_init()
56 create_tlb(tlbix++, MSCC_IO_ORIGIN2_OFFSET, SZ_16M, MMU_REGIO_RW, in vcoreiii_tlb_init()
64 create_tlb(tlbix++, MSCC_FLASH_TO, SZ_16M, MMU_REGIO_RO_C, in vcoreiii_tlb_init()
66 create_tlb(tlbix++, MSCC_FLASH_TO + SZ_32M, SZ_16M, MMU_REGIO_RO_C, in vcoreiii_tlb_init()
74 create_tlb(tlbix++, MSCC_DDR_TO, MSCC_RAM_TLB_SIZE, MMU_REGIO_RW, in vcoreiii_tlb_init()
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/mips/mach-mscc/
H A Dcpu.c43 register int tlbix = 0; in vcoreiii_tlb_init() local
53 create_tlb(tlbix++, MSCC_IO_ORIGIN1_OFFSET, SZ_16M, MMU_REGIO_RW, in vcoreiii_tlb_init()
56 create_tlb(tlbix++, MSCC_IO_ORIGIN2_OFFSET, SZ_16M, MMU_REGIO_RW, in vcoreiii_tlb_init()
64 create_tlb(tlbix++, MSCC_FLASH_TO, SZ_16M, MMU_REGIO_RO_C, in vcoreiii_tlb_init()
66 create_tlb(tlbix++, MSCC_FLASH_TO + SZ_32M, SZ_16M, MMU_REGIO_RO_C, in vcoreiii_tlb_init()
74 create_tlb(tlbix++, MSCC_DDR_TO, MSCC_RAM_TLB_SIZE, MMU_REGIO_RW, in vcoreiii_tlb_init()
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/mips/mach-mscc/
H A Dcpu.c43 register int tlbix = 0; in vcoreiii_tlb_init() local
53 create_tlb(tlbix++, MSCC_IO_ORIGIN1_OFFSET, SZ_16M, MMU_REGIO_RW, in vcoreiii_tlb_init()
56 create_tlb(tlbix++, MSCC_IO_ORIGIN2_OFFSET, SZ_16M, MMU_REGIO_RW, in vcoreiii_tlb_init()
64 create_tlb(tlbix++, MSCC_FLASH_TO, SZ_16M, MMU_REGIO_RO_C, in vcoreiii_tlb_init()
66 create_tlb(tlbix++, MSCC_FLASH_TO + SZ_32M, SZ_16M, MMU_REGIO_RO_C, in vcoreiii_tlb_init()
74 create_tlb(tlbix++, MSCC_DDR_TO, MSCC_RAM_TLB_SIZE, MMU_REGIO_RW, in vcoreiii_tlb_init()
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/mips/mach-mscc/
H A Dcpu.c43 register int tlbix = 0; in vcoreiii_tlb_init() local
53 create_tlb(tlbix++, MSCC_IO_ORIGIN1_OFFSET, SZ_16M, MMU_REGIO_RW, in vcoreiii_tlb_init()
56 create_tlb(tlbix++, MSCC_IO_ORIGIN2_OFFSET, SZ_16M, MMU_REGIO_RW, in vcoreiii_tlb_init()
64 create_tlb(tlbix++, MSCC_FLASH_TO, SZ_16M, MMU_REGIO_RO_C, in vcoreiii_tlb_init()
66 create_tlb(tlbix++, MSCC_FLASH_TO + SZ_32M, SZ_16M, MMU_REGIO_RO_C, in vcoreiii_tlb_init()
74 create_tlb(tlbix++, MSCC_DDR_TO, MSCC_RAM_TLB_SIZE, MMU_REGIO_RW, in vcoreiii_tlb_init()
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/mips/mach-mscc/
H A Dcpu.c43 register int tlbix = 0; in vcoreiii_tlb_init() local
53 create_tlb(tlbix++, MSCC_IO_ORIGIN1_OFFSET, SZ_16M, MMU_REGIO_RW, in vcoreiii_tlb_init()
56 create_tlb(tlbix++, MSCC_IO_ORIGIN2_OFFSET, SZ_16M, MMU_REGIO_RW, in vcoreiii_tlb_init()
64 create_tlb(tlbix++, MSCC_FLASH_TO, SZ_16M, MMU_REGIO_RO_C, in vcoreiii_tlb_init()
66 create_tlb(tlbix++, MSCC_FLASH_TO + SZ_32M, SZ_16M, MMU_REGIO_RO_C, in vcoreiii_tlb_init()
74 create_tlb(tlbix++, MSCC_DDR_TO, MSCC_RAM_TLB_SIZE, MMU_REGIO_RW, in vcoreiii_tlb_init()

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