1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2018 Microsemi Corporation
4 */
5
6 #include <common.h>
7 #include <init.h>
8 #include <asm/global_data.h>
9 #include <linux/bitops.h>
10
11 #include <asm/io.h>
12 #include <asm/types.h>
13 #include <asm/mipsregs.h>
14
15 #include <mach/tlb.h>
16 #include <mach/ddr.h>
17
18 DECLARE_GLOBAL_DATA_PTR;
19
20 #if CONFIG_SYS_SDRAM_SIZE <= SZ_64M
21 #define MSCC_RAM_TLB_SIZE SZ_64M
22 #define MSCC_ATTRIB2 MMU_REGIO_INVAL
23 #elif CONFIG_SYS_SDRAM_SIZE <= SZ_128M
24 #define MSCC_RAM_TLB_SIZE SZ_64M
25 #define MSCC_ATTRIB2 MMU_REGIO_RW
26 #elif CONFIG_SYS_SDRAM_SIZE <= SZ_256M
27 #define MSCC_RAM_TLB_SIZE SZ_256M
28 #define MSCC_ATTRIB2 MMU_REGIO_INVAL
29 #elif CONFIG_SYS_SDRAM_SIZE <= SZ_512M
30 #define MSCC_RAM_TLB_SIZE SZ_256M
31 #define MSCC_ATTRIB2 MMU_REGIO_RW
32 #else
33 #define MSCC_RAM_TLB_SIZE SZ_512M
34 #define MSCC_ATTRIB2 MMU_REGIO_RW
35 #endif
36
37 /* NOTE: lowlevel_init() function does not have access to the
38 * stack. Thus, all called functions must be inlined, and (any) local
39 * variables must be kept in registers.
40 */
vcoreiii_tlb_init(void)41 void vcoreiii_tlb_init(void)
42 {
43 register int tlbix = 0;
44
45 /*
46 * Unlike most of the MIPS based SoCs, the IO register address
47 * are not in KSEG0. The mainline linux kernel built in legacy
48 * mode needs to access some of the registers very early in
49 * the boot and make the assumption that the bootloader has
50 * already configured them, so we have to match this
51 * expectation.
52 */
53 create_tlb(tlbix++, MSCC_IO_ORIGIN1_OFFSET, SZ_16M, MMU_REGIO_RW,
54 MMU_REGIO_RW);
55 #ifdef CONFIG_SOC_LUTON
56 create_tlb(tlbix++, MSCC_IO_ORIGIN2_OFFSET, SZ_16M, MMU_REGIO_RW,
57 MMU_REGIO_RW);
58 #endif
59
60 /*
61 * If U-Boot is located in NOR then we want to be able to use
62 * the data cache in order to boot in a decent duration
63 */
64 create_tlb(tlbix++, MSCC_FLASH_TO, SZ_16M, MMU_REGIO_RO_C,
65 MMU_REGIO_RO_C);
66 create_tlb(tlbix++, MSCC_FLASH_TO + SZ_32M, SZ_16M, MMU_REGIO_RO_C,
67 MMU_REGIO_RO_C);
68
69 /*
70 * Using cache for RAM also helps to improve boot time. Thanks
71 * to this the time to relocate U-Boot in RAM went from 2.092
72 * secs to 0.104 secs.
73 */
74 create_tlb(tlbix++, MSCC_DDR_TO, MSCC_RAM_TLB_SIZE, MMU_REGIO_RW,
75 MSCC_ATTRIB2);
76
77 /* Enable mapping (using TLB) kuseg by clearing the bit ERL,
78 * which is set on reset.
79 */
80 write_c0_status(read_c0_status() & ~ST0_ERL);
81 }
82
mach_cpu_init(void)83 int mach_cpu_init(void)
84 {
85 /* Speed up NOR flash access */
86 #ifdef CONFIG_SOC_LUTON
87 writel(ICPU_PI_MST_CFG_TRISTATE_CTRL +
88 ICPU_PI_MST_CFG_CLK_DIV(4), BASE_CFG + ICPU_PI_MST_CFG);
89
90 writel(ICPU_SPI_MST_CFG_FAST_READ_ENA +
91 ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) +
92 ICPU_SPI_MST_CFG_CLK_DIV(9), BASE_CFG + ICPU_SPI_MST_CFG);
93 #else
94 #if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_SERVAL)
95 writel(ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) +
96 ICPU_SPI_MST_CFG_CLK_DIV(9), BASE_CFG + ICPU_SPI_MST_CFG);
97 #endif
98 #if defined(CONFIG_SOC_JR2) || defined(CONFIG_SOC_SERVALT)
99 writel(ICPU_SPI_MST_CFG_FAST_READ_ENA +
100 ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) +
101 ICPU_SPI_MST_CFG_CLK_DIV(14), BASE_CFG + ICPU_SPI_MST_CFG);
102 #endif
103 /*
104 * Legacy and mainline linux kernel expect that the
105 * interruption map was set as it was done by redboot.
106 */
107 writel(~0, BASE_CFG + ICPU_DST_INTR_MAP(0));
108 writel(0, BASE_CFG + ICPU_DST_INTR_MAP(1));
109 writel(0, BASE_CFG + ICPU_DST_INTR_MAP(2));
110 writel(0, BASE_CFG + ICPU_DST_INTR_MAP(3));
111 #endif
112 return 0;
113 }
114