/dports/www/firefox/firefox-99.0/third_party/jpeg-xl/lib/jxl/ |
H A D | fast_dct16-inl.h | 120 int16x8_t v94 = vsubq_s16(v92, v93); in FastIDCT() local 121 int16x8_t v95 = vaddq_s16(v91, v94); in FastIDCT() 141 int16x8_t v113 = vsubq_s16(v91, v94); in FastIDCT()
|
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/AMDGPU/ |
H A D | reserve-vgpr-for-sgpr-spill.ll | 33 ,~{v90},~{v91},~{v92},~{v93},~{v94},~{v95},~{v96},~{v97},~{v98},~{v99} 78 ,~{v90},~{v91},~{v92},~{v93},~{v94},~{v95},~{v96},~{v97},~{v98},~{v99} 120 ,~{v90},~{v91},~{v92},~{v93},~{v94},~{v95},~{v96},~{v97},~{v98},~{v99} 169 ,~{v90},~{v91},~{v92},~{v93},~{v94},~{v95},~{v96},~{v97},~{v98},~{v99}
|
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/Hexagon/ |
H A D | fltnvjump.ll | 155 %v94 = phi i16 [ %v92, %b10 ], [ 1, %b7 ] 157 store i16 %v94, i16* %v95, align 2, !tbaa !4 158 %v96 = sext i16 %v94 to i32 168 call void @f6(i16* %v100, i16 signext %v94, i16* %v101, i16 signext %v102)
|
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/Hexagon/ |
H A D | fltnvjump.ll | 155 %v94 = phi i16 [ %v92, %b10 ], [ 1, %b7 ] 157 store i16 %v94, i16* %v95, align 2, !tbaa !4 158 %v96 = sext i16 %v94 to i32 168 call void @f6(i16* %v100, i16 signext %v94, i16* %v101, i16 signext %v102)
|
H A D | swp-phi.ll | 68 %v54 = phi float [ %v29, %b0 ], [ %v94, %b1 ] 108 %v94 = fadd float %v54, %v93 136 store float %v94, float* %v12, align 4
|
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/Hexagon/ |
H A D | fltnvjump.ll | 155 %v94 = phi i16 [ %v92, %b10 ], [ 1, %b7 ] 157 store i16 %v94, i16* %v95, align 2, !tbaa !4 158 %v96 = sext i16 %v94 to i32 168 call void @f6(i16* %v100, i16 signext %v94, i16* %v101, i16 signext %v102)
|
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/Hexagon/ |
H A D | fltnvjump.ll | 155 %v94 = phi i16 [ %v92, %b10 ], [ 1, %b7 ] 157 store i16 %v94, i16* %v95, align 2, !tbaa !4 158 %v96 = sext i16 %v94 to i32 168 call void @f6(i16* %v100, i16 signext %v94, i16* %v101, i16 signext %v102)
|
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/Hexagon/ |
H A D | fltnvjump.ll | 155 %v94 = phi i16 [ %v92, %b10 ], [ 1, %b7 ] 157 store i16 %v94, i16* %v95, align 2, !tbaa !4 158 %v96 = sext i16 %v94 to i32 168 call void @f6(i16* %v100, i16 signext %v94, i16* %v101, i16 signext %v102)
|
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/Hexagon/ |
H A D | fltnvjump.ll | 155 %v94 = phi i16 [ %v92, %b10 ], [ 1, %b7 ] 157 store i16 %v94, i16* %v95, align 2, !tbaa !4 158 %v96 = sext i16 %v94 to i32 168 call void @f6(i16* %v100, i16 signext %v94, i16* %v101, i16 signext %v102)
|
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/Hexagon/ |
H A D | fltnvjump.ll | 155 %v94 = phi i16 [ %v92, %b10 ], [ 1, %b7 ] 157 store i16 %v94, i16* %v95, align 2, !tbaa !4 158 %v96 = sext i16 %v94 to i32 168 call void @f6(i16* %v100, i16 signext %v94, i16* %v101, i16 signext %v102)
|
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/ |
H A D | reserve-vgpr-for-sgpr-spill.ll | 33 ,~{v90},~{v91},~{v92},~{v93},~{v94},~{v95},~{v96},~{v97},~{v98},~{v99} 78 ,~{v90},~{v91},~{v92},~{v93},~{v94},~{v95},~{v96},~{v97},~{v98},~{v99} 120 ,~{v90},~{v91},~{v92},~{v93},~{v94},~{v95},~{v96},~{v97},~{v98},~{v99} 169 ,~{v90},~{v91},~{v92},~{v93},~{v94},~{v95},~{v96},~{v97},~{v98},~{v99}
|
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/Hexagon/ |
H A D | fltnvjump.ll | 155 %v94 = phi i16 [ %v92, %b10 ], [ 1, %b7 ] 157 store i16 %v94, i16* %v95, align 2, !tbaa !4 158 %v96 = sext i16 %v94 to i32 168 call void @f6(i16* %v100, i16 signext %v94, i16* %v101, i16 signext %v102)
|
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/Hexagon/ |
H A D | fltnvjump.ll | 155 %v94 = phi i16 [ %v92, %b10 ], [ 1, %b7 ] 157 store i16 %v94, i16* %v95, align 2, !tbaa !4 158 %v96 = sext i16 %v94 to i32 168 call void @f6(i16* %v100, i16 signext %v94, i16* %v101, i16 signext %v102)
|
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/Hexagon/ |
H A D | fltnvjump.ll | 155 %v94 = phi i16 [ %v92, %b10 ], [ 1, %b7 ] 157 store i16 %v94, i16* %v95, align 2, !tbaa !4 158 %v96 = sext i16 %v94 to i32 168 call void @f6(i16* %v100, i16 signext %v94, i16* %v101, i16 signext %v102)
|
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/Hexagon/ |
H A D | fltnvjump.ll | 155 %v94 = phi i16 [ %v92, %b10 ], [ 1, %b7 ] 157 store i16 %v94, i16* %v95, align 2, !tbaa !4 158 %v96 = sext i16 %v94 to i32 168 call void @f6(i16* %v100, i16 signext %v94, i16* %v101, i16 signext %v102)
|
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/ |
H A D | reserve-vgpr-for-sgpr-spill.ll | 33 ,~{v90},~{v91},~{v92},~{v93},~{v94},~{v95},~{v96},~{v97},~{v98},~{v99} 78 ,~{v90},~{v91},~{v92},~{v93},~{v94},~{v95},~{v96},~{v97},~{v98},~{v99} 120 ,~{v90},~{v91},~{v92},~{v93},~{v94},~{v95},~{v96},~{v97},~{v98},~{v99} 169 ,~{v90},~{v91},~{v92},~{v93},~{v94},~{v95},~{v96},~{v97},~{v98},~{v99}
|
/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/Hexagon/ |
H A D | fltnvjump.ll | 155 %v94 = phi i16 [ %v92, %b10 ], [ 1, %b7 ] 157 store i16 %v94, i16* %v95, align 2, !tbaa !4 158 %v96 = sext i16 %v94 to i32 168 call void @f6(i16* %v100, i16 signext %v94, i16* %v101, i16 signext %v102)
|
/dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/Hexagon/ |
H A D | fltnvjump.ll | 155 %v94 = phi i16 [ %v92, %b10 ], [ 1, %b7 ] 157 store i16 %v94, i16* %v95, align 2, !tbaa !4 158 %v96 = sext i16 %v94 to i32 168 call void @f6(i16* %v100, i16 signext %v94, i16* %v101, i16 signext %v102)
|
/dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/Hexagon/ |
H A D | fltnvjump.ll | 155 %v94 = phi i16 [ %v92, %b10 ], [ 1, %b7 ] 157 store i16 %v94, i16* %v95, align 2, !tbaa !4 158 %v96 = sext i16 %v94 to i32 168 call void @f6(i16* %v100, i16 signext %v94, i16* %v101, i16 signext %v102)
|
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/Hexagon/ |
H A D | fltnvjump.ll | 155 %v94 = phi i16 [ %v92, %b10 ], [ 1, %b7 ] 157 store i16 %v94, i16* %v95, align 2, !tbaa !4 158 %v96 = sext i16 %v94 to i32 168 call void @f6(i16* %v100, i16 signext %v94, i16* %v101, i16 signext %v102)
|
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AMDGPU/ |
H A D | reserve-vgpr-for-sgpr-spill.ll | 33 ,~{v90},~{v91},~{v92},~{v93},~{v94},~{v95},~{v96},~{v97},~{v98},~{v99} 78 ,~{v90},~{v91},~{v92},~{v93},~{v94},~{v95},~{v96},~{v97},~{v98},~{v99} 120 ,~{v90},~{v91},~{v92},~{v93},~{v94},~{v95},~{v96},~{v97},~{v98},~{v99} 169 ,~{v90},~{v91},~{v92},~{v93},~{v94},~{v95},~{v96},~{v97},~{v98},~{v99} 212 ,~{v90},~{v91},~{v92},~{v93},~{v94},~{v95},~{v96},~{v97},~{v98},~{v99}
|
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/ |
H A D | reserve-vgpr-for-sgpr-spill.ll | 33 ,~{v90},~{v91},~{v92},~{v93},~{v94},~{v95},~{v96},~{v97},~{v98},~{v99} 78 ,~{v90},~{v91},~{v92},~{v93},~{v94},~{v95},~{v96},~{v97},~{v98},~{v99} 120 ,~{v90},~{v91},~{v92},~{v93},~{v94},~{v95},~{v96},~{v97},~{v98},~{v99} 169 ,~{v90},~{v91},~{v92},~{v93},~{v94},~{v95},~{v96},~{v97},~{v98},~{v99} 212 ,~{v90},~{v91},~{v92},~{v93},~{v94},~{v95},~{v96},~{v97},~{v98},~{v99}
|
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AMDGPU/ |
H A D | reserve-vgpr-for-sgpr-spill.ll | 33 ,~{v90},~{v91},~{v92},~{v93},~{v94},~{v95},~{v96},~{v97},~{v98},~{v99} 78 ,~{v90},~{v91},~{v92},~{v93},~{v94},~{v95},~{v96},~{v97},~{v98},~{v99} 120 ,~{v90},~{v91},~{v92},~{v93},~{v94},~{v95},~{v96},~{v97},~{v98},~{v99} 169 ,~{v90},~{v91},~{v92},~{v93},~{v94},~{v95},~{v96},~{v97},~{v98},~{v99} 212 ,~{v90},~{v91},~{v92},~{v93},~{v94},~{v95},~{v96},~{v97},~{v98},~{v99}
|
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/ |
H A D | reserve-vgpr-for-sgpr-spill.ll | 33 ,~{v90},~{v91},~{v92},~{v93},~{v94},~{v95},~{v96},~{v97},~{v98},~{v99} 78 ,~{v90},~{v91},~{v92},~{v93},~{v94},~{v95},~{v96},~{v97},~{v98},~{v99} 120 ,~{v90},~{v91},~{v92},~{v93},~{v94},~{v95},~{v96},~{v97},~{v98},~{v99} 169 ,~{v90},~{v91},~{v92},~{v93},~{v94},~{v95},~{v96},~{v97},~{v98},~{v99} 212 ,~{v90},~{v91},~{v92},~{v93},~{v94},~{v95},~{v96},~{v97},~{v98},~{v99}
|
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/ |
H A D | reserve-vgpr-for-sgpr-spill.ll | 33 ,~{v90},~{v91},~{v92},~{v93},~{v94},~{v95},~{v96},~{v97},~{v98},~{v99} 78 ,~{v90},~{v91},~{v92},~{v93},~{v94},~{v95},~{v96},~{v97},~{v98},~{v99} 120 ,~{v90},~{v91},~{v92},~{v93},~{v94},~{v95},~{v96},~{v97},~{v98},~{v99} 169 ,~{v90},~{v91},~{v92},~{v93},~{v94},~{v95},~{v96},~{v97},~{v98},~{v99} 212 ,~{v90},~{v91},~{v92},~{v93},~{v94},~{v95},~{v96},~{v97},~{v98},~{v99}
|