/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/AMDGPU/ |
H A D | bypass-div.ll | 59 ; GFX9-NEXT: v_addc_co_u32_e64 v10, vcc, v7, v11, s[4:5] 80 ; GFX9-NEXT: v_addc_co_u32_e64 v7, vcc, v7, v8, s[4:5] 120 ; GFX9-NEXT: v_addc_co_u32_e64 v13, s[4:5], 0, v7, s[4:5] 125 ; GFX9-NEXT: v_addc_co_u32_e64 v15, s[4:5], 0, v7, s[4:5] 220 ; GFX9-NEXT: v_addc_co_u32_e64 v8, vcc, v5, v9, s[4:5] 241 ; GFX9-NEXT: v_addc_co_u32_e64 v5, vcc, v5, v7, s[4:5] 377 ; GFX9-NEXT: v_addc_co_u32_e64 v9, vcc, v6, v10, s[4:5] 398 ; GFX9-NEXT: v_addc_co_u32_e64 v6, vcc, v6, v8, s[4:5] 534 ; GFX9-NEXT: v_addc_co_u32_e64 v8, vcc, v5, v9, s[4:5] 555 ; GFX9-NEXT: v_addc_co_u32_e64 v5, vcc, v5, v7, s[4:5] [all …]
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H A D | idiv-licm.ll | 260 ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1] 266 ; GFX9-NEXT: v_addc_co_u32_e64 v2, s[0:1], 0, v7, s[0:1] 315 ; GFX9-NEXT: v_addc_co_u32_e64 v8, s[2:3], 0, v10, s[2:3] 319 ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1] 363 ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1] 432 ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v8, v6, s[0:1]
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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/AMDGPU/ |
H A D | bypass-div.ll | 59 ; GFX9-NEXT: v_addc_co_u32_e64 v10, vcc, v7, v11, s[4:5] 80 ; GFX9-NEXT: v_addc_co_u32_e64 v7, vcc, v7, v8, s[4:5] 120 ; GFX9-NEXT: v_addc_co_u32_e64 v13, s[4:5], 0, v7, s[4:5] 125 ; GFX9-NEXT: v_addc_co_u32_e64 v15, s[4:5], 0, v7, s[4:5] 220 ; GFX9-NEXT: v_addc_co_u32_e64 v8, vcc, v5, v9, s[4:5] 241 ; GFX9-NEXT: v_addc_co_u32_e64 v5, vcc, v5, v7, s[4:5] 377 ; GFX9-NEXT: v_addc_co_u32_e64 v9, vcc, v6, v10, s[4:5] 398 ; GFX9-NEXT: v_addc_co_u32_e64 v6, vcc, v6, v8, s[4:5] 534 ; GFX9-NEXT: v_addc_co_u32_e64 v8, vcc, v5, v9, s[4:5] 555 ; GFX9-NEXT: v_addc_co_u32_e64 v5, vcc, v5, v7, s[4:5] [all …]
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H A D | idiv-licm.ll | 260 ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1] 266 ; GFX9-NEXT: v_addc_co_u32_e64 v2, s[0:1], 0, v7, s[0:1] 309 ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1] 316 ; GFX9-NEXT: v_addc_co_u32_e64 v7, s[0:1], 0, v9, s[0:1] 363 ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1] 417 ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v8, v6, s[0:1]
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/ |
H A D | bypass-div.ll | 58 ; GFX9-NEXT: v_addc_co_u32_e64 v9, vcc, v6, v10, s[4:5] 79 ; GFX9-NEXT: v_addc_co_u32_e64 v6, vcc, v6, v8, s[4:5] 119 ; GFX9-NEXT: v_addc_co_u32_e64 v11, s[4:5], 0, v6, s[4:5] 124 ; GFX9-NEXT: v_addc_co_u32_e64 v13, s[4:5], 0, v6, s[4:5] 221 ; GFX9-NEXT: v_addc_co_u32_e64 v8, vcc, v5, v9, s[4:5] 242 ; GFX9-NEXT: v_addc_co_u32_e64 v5, vcc, v5, v7, s[4:5] 379 ; GFX9-NEXT: v_addc_co_u32_e64 v8, vcc, v5, v9, s[4:5] 400 ; GFX9-NEXT: v_addc_co_u32_e64 v5, vcc, v5, v7, s[4:5] 538 ; GFX9-NEXT: v_addc_co_u32_e64 v8, vcc, v5, v9, s[4:5] 559 ; GFX9-NEXT: v_addc_co_u32_e64 v5, vcc, v5, v7, s[4:5] [all …]
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H A D | idiv-licm.ll | 429 ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1] 435 ; GFX9-NEXT: v_addc_co_u32_e64 v2, s[0:1], 0, v7, s[0:1] 517 ; GFX9-NEXT: v_addc_co_u32_e64 v8, s[2:3], 0, v10, s[2:3] 521 ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1] 600 ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1] 706 ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v8, v6, s[0:1]
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H A D | global-load-saddr-to-vaddr.ll | 32 ; GCN-NEXT: v_addc_co_u32_e64 v2, s[0:1], 0, v2, s[0:1]
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AMDGPU/ |
H A D | bypass-div.ll | 58 ; GFX9-NEXT: v_addc_co_u32_e64 v9, vcc, v6, v10, s[4:5] 79 ; GFX9-NEXT: v_addc_co_u32_e64 v6, vcc, v6, v8, s[4:5] 119 ; GFX9-NEXT: v_addc_co_u32_e64 v11, s[4:5], 0, v6, s[4:5] 124 ; GFX9-NEXT: v_addc_co_u32_e64 v13, s[4:5], 0, v6, s[4:5] 221 ; GFX9-NEXT: v_addc_co_u32_e64 v8, vcc, v5, v9, s[4:5] 242 ; GFX9-NEXT: v_addc_co_u32_e64 v5, vcc, v5, v7, s[4:5] 379 ; GFX9-NEXT: v_addc_co_u32_e64 v8, vcc, v5, v9, s[4:5] 400 ; GFX9-NEXT: v_addc_co_u32_e64 v5, vcc, v5, v7, s[4:5] 538 ; GFX9-NEXT: v_addc_co_u32_e64 v8, vcc, v5, v9, s[4:5] 559 ; GFX9-NEXT: v_addc_co_u32_e64 v5, vcc, v5, v7, s[4:5] [all …]
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H A D | idiv-licm.ll | 429 ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1] 435 ; GFX9-NEXT: v_addc_co_u32_e64 v2, s[0:1], 0, v7, s[0:1] 517 ; GFX9-NEXT: v_addc_co_u32_e64 v8, s[2:3], 0, v10, s[2:3] 521 ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1] 600 ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1] 706 ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v8, v6, s[0:1]
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H A D | global-load-saddr-to-vaddr.ll | 32 ; GCN-NEXT: v_addc_co_u32_e64 v2, s[0:1], 0, v2, s[0:1]
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/ |
H A D | bypass-div.ll | 59 ; GFX9-NEXT: v_addc_co_u32_e64 v10, vcc, v7, v11, s[4:5] 80 ; GFX9-NEXT: v_addc_co_u32_e64 v7, vcc, v7, v8, s[4:5] 120 ; GFX9-NEXT: v_addc_co_u32_e64 v13, s[4:5], 0, v7, s[4:5] 125 ; GFX9-NEXT: v_addc_co_u32_e64 v15, s[4:5], 0, v7, s[4:5] 220 ; GFX9-NEXT: v_addc_co_u32_e64 v8, vcc, v5, v9, s[4:5] 241 ; GFX9-NEXT: v_addc_co_u32_e64 v5, vcc, v5, v7, s[4:5] 377 ; GFX9-NEXT: v_addc_co_u32_e64 v9, vcc, v6, v10, s[4:5] 398 ; GFX9-NEXT: v_addc_co_u32_e64 v6, vcc, v6, v8, s[4:5] 534 ; GFX9-NEXT: v_addc_co_u32_e64 v8, vcc, v5, v9, s[4:5] 555 ; GFX9-NEXT: v_addc_co_u32_e64 v5, vcc, v5, v7, s[4:5] [all …]
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H A D | idiv-licm.ll | 258 ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1] 264 ; GFX9-NEXT: v_addc_co_u32_e64 v2, s[0:1], 0, v7, s[0:1] 313 ; GFX9-NEXT: v_addc_co_u32_e64 v8, s[2:3], 0, v10, s[2:3] 317 ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1] 361 ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1] 430 ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v8, v6, s[0:1]
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/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/AMDGPU/ |
H A D | bypass-div.ll | 59 ; GFX9-NEXT: v_addc_co_u32_e64 v10, vcc, v7, v11, s[4:5] 80 ; GFX9-NEXT: v_addc_co_u32_e64 v7, vcc, v7, v8, s[4:5] 120 ; GFX9-NEXT: v_addc_co_u32_e64 v13, s[4:5], 0, v7, s[4:5] 125 ; GFX9-NEXT: v_addc_co_u32_e64 v15, s[4:5], 0, v7, s[4:5] 220 ; GFX9-NEXT: v_addc_co_u32_e64 v8, vcc, v5, v9, s[4:5] 241 ; GFX9-NEXT: v_addc_co_u32_e64 v5, vcc, v5, v7, s[4:5] 377 ; GFX9-NEXT: v_addc_co_u32_e64 v9, vcc, v6, v10, s[4:5] 398 ; GFX9-NEXT: v_addc_co_u32_e64 v6, vcc, v6, v8, s[4:5] 534 ; GFX9-NEXT: v_addc_co_u32_e64 v8, vcc, v5, v9, s[4:5] 555 ; GFX9-NEXT: v_addc_co_u32_e64 v5, vcc, v5, v7, s[4:5] [all …]
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H A D | idiv-licm.ll | 260 ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1] 266 ; GFX9-NEXT: v_addc_co_u32_e64 v2, s[0:1], 0, v7, s[0:1] 309 ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1] 316 ; GFX9-NEXT: v_addc_co_u32_e64 v7, s[0:1], 0, v9, s[0:1] 363 ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1] 417 ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v8, v6, s[0:1]
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AMDGPU/ |
H A D | bypass-div.ll | 58 ; GFX9-NEXT: v_addc_co_u32_e64 v9, vcc, v6, v10, s[4:5] 79 ; GFX9-NEXT: v_addc_co_u32_e64 v6, vcc, v6, v8, s[4:5] 119 ; GFX9-NEXT: v_addc_co_u32_e64 v11, s[4:5], 0, v6, s[4:5] 124 ; GFX9-NEXT: v_addc_co_u32_e64 v13, s[4:5], 0, v6, s[4:5] 221 ; GFX9-NEXT: v_addc_co_u32_e64 v8, vcc, v5, v9, s[4:5] 242 ; GFX9-NEXT: v_addc_co_u32_e64 v5, vcc, v5, v7, s[4:5] 379 ; GFX9-NEXT: v_addc_co_u32_e64 v8, vcc, v5, v9, s[4:5] 400 ; GFX9-NEXT: v_addc_co_u32_e64 v5, vcc, v5, v7, s[4:5] 538 ; GFX9-NEXT: v_addc_co_u32_e64 v8, vcc, v5, v9, s[4:5] 559 ; GFX9-NEXT: v_addc_co_u32_e64 v5, vcc, v5, v7, s[4:5] [all …]
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H A D | idiv-licm.ll | 428 ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1] 435 ; GFX9-NEXT: v_addc_co_u32_e64 v0, s[0:1], 0, v7, s[0:1] 516 ; GFX9-NEXT: v_addc_co_u32_e64 v8, s[2:3], 0, v10, s[2:3] 520 ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1] 600 ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1] 705 ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v8, v6, s[0:1]
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H A D | global-load-saddr-to-vaddr.ll | 32 ; GCN-NEXT: v_addc_co_u32_e64 v1, s[0:1], 0, v1, s[0:1]
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/ |
H A D | bypass-div.ll | 58 ; GFX9-NEXT: v_addc_co_u32_e64 v9, vcc, v6, v10, s[4:5] 79 ; GFX9-NEXT: v_addc_co_u32_e64 v6, vcc, v6, v8, s[4:5] 119 ; GFX9-NEXT: v_addc_co_u32_e64 v11, s[4:5], 0, v6, s[4:5] 124 ; GFX9-NEXT: v_addc_co_u32_e64 v13, s[4:5], 0, v6, s[4:5] 221 ; GFX9-NEXT: v_addc_co_u32_e64 v8, vcc, v5, v9, s[4:5] 242 ; GFX9-NEXT: v_addc_co_u32_e64 v5, vcc, v5, v7, s[4:5] 379 ; GFX9-NEXT: v_addc_co_u32_e64 v8, vcc, v5, v9, s[4:5] 400 ; GFX9-NEXT: v_addc_co_u32_e64 v5, vcc, v5, v7, s[4:5] 538 ; GFX9-NEXT: v_addc_co_u32_e64 v8, vcc, v5, v9, s[4:5] 559 ; GFX9-NEXT: v_addc_co_u32_e64 v5, vcc, v5, v7, s[4:5] [all …]
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H A D | idiv-licm.ll | 429 ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1] 435 ; GFX9-NEXT: v_addc_co_u32_e64 v2, s[0:1], 0, v7, s[0:1] 517 ; GFX9-NEXT: v_addc_co_u32_e64 v8, s[2:3], 0, v10, s[2:3] 521 ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1] 600 ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1] 706 ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v8, v6, s[0:1]
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/ |
H A D | bypass-div.ll | 59 ; GFX9-NEXT: v_addc_co_u32_e64 v10, vcc, v7, v11, s[4:5] 80 ; GFX9-NEXT: v_addc_co_u32_e64 v7, vcc, v7, v8, s[4:5] 120 ; GFX9-NEXT: v_addc_co_u32_e64 v13, s[4:5], 0, v7, s[4:5] 125 ; GFX9-NEXT: v_addc_co_u32_e64 v15, s[4:5], 0, v7, s[4:5] 220 ; GFX9-NEXT: v_addc_co_u32_e64 v8, vcc, v5, v9, s[4:5] 241 ; GFX9-NEXT: v_addc_co_u32_e64 v5, vcc, v5, v7, s[4:5] 377 ; GFX9-NEXT: v_addc_co_u32_e64 v9, vcc, v6, v10, s[4:5] 398 ; GFX9-NEXT: v_addc_co_u32_e64 v6, vcc, v6, v8, s[4:5] 534 ; GFX9-NEXT: v_addc_co_u32_e64 v8, vcc, v5, v9, s[4:5] 555 ; GFX9-NEXT: v_addc_co_u32_e64 v5, vcc, v5, v7, s[4:5] [all …]
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H A D | idiv-licm.ll | 258 ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1] 264 ; GFX9-NEXT: v_addc_co_u32_e64 v2, s[0:1], 0, v7, s[0:1] 313 ; GFX9-NEXT: v_addc_co_u32_e64 v8, s[2:3], 0, v10, s[2:3] 317 ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1] 361 ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1] 430 ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v8, v6, s[0:1]
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/ |
H A D | bypass-div.ll | 58 ; GFX9-NEXT: v_addc_co_u32_e64 v9, vcc, v6, v10, s[4:5] 79 ; GFX9-NEXT: v_addc_co_u32_e64 v6, vcc, v6, v8, s[4:5] 119 ; GFX9-NEXT: v_addc_co_u32_e64 v11, s[4:5], 0, v6, s[4:5] 124 ; GFX9-NEXT: v_addc_co_u32_e64 v13, s[4:5], 0, v6, s[4:5] 221 ; GFX9-NEXT: v_addc_co_u32_e64 v8, vcc, v5, v9, s[4:5] 242 ; GFX9-NEXT: v_addc_co_u32_e64 v5, vcc, v5, v7, s[4:5] 379 ; GFX9-NEXT: v_addc_co_u32_e64 v8, vcc, v5, v9, s[4:5] 400 ; GFX9-NEXT: v_addc_co_u32_e64 v5, vcc, v5, v7, s[4:5] 538 ; GFX9-NEXT: v_addc_co_u32_e64 v8, vcc, v5, v9, s[4:5] 559 ; GFX9-NEXT: v_addc_co_u32_e64 v5, vcc, v5, v7, s[4:5] [all …]
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H A D | idiv-licm.ll | 429 ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1] 435 ; GFX9-NEXT: v_addc_co_u32_e64 v2, s[0:1], 0, v7, s[0:1] 517 ; GFX9-NEXT: v_addc_co_u32_e64 v8, s[2:3], 0, v10, s[2:3] 521 ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1] 600 ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1] 706 ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v8, v6, s[0:1]
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/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/AMDGPU/ |
H A D | idiv-licm.ll | 282 ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v2, v6, s[0:1] 290 ; GFX9-NEXT: v_addc_co_u32_e64 v2, s[0:1], 0, v8, s[0:1] 333 ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v8, v6, s[0:1] 340 ; GFX9-NEXT: v_addc_co_u32_e64 v7, s[0:1], 0, v9, s[0:1] 387 ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1] 441 ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v8, v6, s[0:1]
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/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/AMDGPU/ |
H A D | idiv-licm.ll | 282 ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v2, v6, s[0:1] 290 ; GFX9-NEXT: v_addc_co_u32_e64 v2, s[0:1], 0, v8, s[0:1] 333 ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v8, v6, s[0:1] 340 ; GFX9-NEXT: v_addc_co_u32_e64 v7, s[0:1], 0, v9, s[0:1] 387 ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1] 441 ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v8, v6, s[0:1]
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