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Searched refs:v_mad_u64_u32 (Results 1 – 25 of 301) sorted by relevance

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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/AMDGPU/
H A Dmad_64_32.ll35 ; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v0, v1, v[2:3]
50 ; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v0, v1, v[2:3]
70 ; CI: v_mad_u64_u32
71 ; CI: v_mad_u64_u32
73 ; CI: v_mad_u64_u32
90 ; SI-NOT: v_mad_u64_u32
114 ; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v0, v2, v[4:5]
158 ; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v1, v0, v[0:1]
159 ; SI-NOT: v_mad_u64_u32
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/AMDGPU/
H A Dmad_64_32.ll35 ; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v0, v1, v[2:3]
50 ; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v0, v1, v[2:3]
70 ; CI: v_mad_u64_u32
71 ; CI: v_mad_u64_u32
73 ; CI: v_mad_u64_u32
90 ; SI-NOT: v_mad_u64_u32
114 ; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v0, v2, v[4:5]
158 ; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v1, v0, v[0:1]
159 ; SI-NOT: v_mad_u64_u32
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/AMDGPU/
H A Dmad_64_32.ll35 ; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v0, v1, v[2:3]
50 ; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v0, v1, v[2:3]
70 ; CI: v_mad_u64_u32
71 ; CI: v_mad_u64_u32
73 ; CI: v_mad_u64_u32
90 ; SI-NOT: v_mad_u64_u32
114 ; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v0, v2, v[4:5]
158 ; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v1, v0, v[0:1]
159 ; SI-NOT: v_mad_u64_u32
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dmad_64_32.ll35 ; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v0, v1, v[2:3]
50 ; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v0, v1, v[2:3]
70 ; CI: v_mad_u64_u32
71 ; CI: v_mad_u64_u32
73 ; CI: v_mad_u64_u32
90 ; SI-NOT: v_mad_u64_u32
114 ; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v0, v2, v[4:5]
158 ; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v1, v0, v[0:1]
159 ; SI-NOT: v_mad_u64_u32
H A Ddag-divergence-atomic.ll19 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, 12, v[0:1]
41 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, 12, v[0:1]
63 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, 12, v[0:1]
85 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, 12, v[0:1]
107 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, 12, v[0:1]
141 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v0, 12, s[2:3]
163 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, 12, v[0:1]
185 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, 12, v[0:1]
207 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, 12, v[0:1]
229 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, 12, v[0:1]
[all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AMDGPU/
H A Dmad_64_32.ll35 ; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v0, v1, v[2:3]
50 ; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v0, v1, v[2:3]
70 ; CI: v_mad_u64_u32
71 ; CI: v_mad_u64_u32
73 ; CI: v_mad_u64_u32
90 ; SI-NOT: v_mad_u64_u32
114 ; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v0, v2, v[4:5]
158 ; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v1, v0, v[0:1]
159 ; SI-NOT: v_mad_u64_u32
H A Ddag-divergence-atomic.ll19 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, 12, v[0:1]
41 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, 12, v[0:1]
63 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, 12, v[0:1]
85 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, 12, v[0:1]
107 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, 12, v[0:1]
141 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v0, 12, s[2:3]
163 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, 12, v[0:1]
185 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, 12, v[0:1]
207 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, 12, v[0:1]
229 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, 12, v[0:1]
[all …]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dmad_64_32.ll35 ; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v0, v1, v[2:3]
50 ; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v0, v1, v[2:3]
70 ; CI: v_mad_u64_u32
71 ; CI: v_mad_u64_u32
73 ; CI: v_mad_u64_u32
90 ; SI-NOT: v_mad_u64_u32
114 ; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v0, v2, v[4:5]
158 ; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v1, v0, v[0:1]
159 ; SI-NOT: v_mad_u64_u32
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/AMDGPU/
H A Dmad_64_32.ll35 ; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v0, v1, v[2:3]
50 ; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v0, v1, v[2:3]
70 ; CI: v_mad_u64_u32
71 ; CI: v_mad_u64_u32
73 ; CI: v_mad_u64_u32
90 ; SI-NOT: v_mad_u64_u32
114 ; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v0, v2, v[4:5]
158 ; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v1, v0, v[0:1]
159 ; SI-NOT: v_mad_u64_u32
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AMDGPU/
H A Dmad_64_32.ll35 ; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v0, v1, v[2:3]
50 ; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v0, v1, v[2:3]
70 ; CI: v_mad_u64_u32
71 ; CI: v_mad_u64_u32
73 ; CI: v_mad_u64_u32
90 ; SI-NOT: v_mad_u64_u32
114 ; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v0, v2, v[4:5]
158 ; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v1, v0, v[0:1]
159 ; SI-NOT: v_mad_u64_u32
H A Ddag-divergence-atomic.ll19 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, 12, v[0:1]
41 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, 12, v[0:1]
63 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, 12, v[0:1]
85 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, 12, v[0:1]
107 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, 12, v[0:1]
141 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v0, 12, s[2:3]
163 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, 12, v[0:1]
185 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, 12, v[0:1]
207 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, 12, v[0:1]
229 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, 12, v[0:1]
[all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dmad_64_32.ll35 ; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v0, v1, v[2:3]
50 ; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v0, v1, v[2:3]
70 ; CI: v_mad_u64_u32
71 ; CI: v_mad_u64_u32
73 ; CI: v_mad_u64_u32
90 ; SI-NOT: v_mad_u64_u32
114 ; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v0, v2, v[4:5]
158 ; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v1, v0, v[0:1]
159 ; SI-NOT: v_mad_u64_u32
H A Ddag-divergence-atomic.ll19 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, 12, v[0:1]
41 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, 12, v[0:1]
63 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, 12, v[0:1]
85 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, 12, v[0:1]
107 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, 12, v[0:1]
141 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v0, 12, s[2:3]
163 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, 12, v[0:1]
185 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, 12, v[0:1]
207 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, 12, v[0:1]
229 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, 12, v[0:1]
[all …]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dmad_64_32.ll35 ; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v0, v1, v[2:3]
50 ; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v0, v1, v[2:3]
70 ; CI: v_mad_u64_u32
71 ; CI: v_mad_u64_u32
73 ; CI: v_mad_u64_u32
90 ; SI-NOT: v_mad_u64_u32
114 ; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v0, v2, v[4:5]
158 ; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v1, v0, v[0:1]
159 ; SI-NOT: v_mad_u64_u32
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/AMDGPU/
H A Dmad_64_32.ll35 ; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v0, v1, v[2:3]
50 ; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v0, v1, v[2:3]
70 ; CI: v_mad_u64_u32
71 ; CI: v_mad_u64_u32
73 ; CI: v_mad_u64_u32
90 ; SI-NOT: v_mad_u64_u32
114 ; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v0, v2, v[4:5]
158 ; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v1, v0, v[0:1]
159 ; SI-NOT: v_mad_u64_u32
/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/AMDGPU/
H A Dmad_64_32.ll35 ; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v0, v1, v[2:3]
50 ; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v0, v1, v[2:3]
70 ; CI: v_mad_u64_u32
71 ; CI: v_mad_u64_u32
73 ; CI: v_mad_u64_u32
90 ; SI-NOT: v_mad_u64_u32
114 ; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v0, v2, v[4:5]
158 ; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v1, v0, v[0:1]
159 ; SI-NOT: v_mad_u64_u32
/dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/AMDGPU/
H A Dmad_64_32.ll35 ; CI: v_mad_u64_u32 v[0:1], s[6:7], v0, v1, v[2:3]
50 ; CI: v_mad_u64_u32 v[0:1], s[6:7], v0, v1, v[2:3]
70 ; CI: v_mad_u64_u32
71 ; CI: v_mad_u64_u32
73 ; CI: v_mad_u64_u32
90 ; SI-NOT: v_mad_u64_u32
114 ; CI: v_mad_u64_u32 v[0:1], s[6:7], v0, v2, v[4:5]
158 ; CI: v_mad_u64_u32 v[0:1], s[6:7], v1, v0, v[0:1]
159 ; SI-NOT: v_mad_u64_u32
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dmad_64_32.ll35 ; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v0, v1, v[2:3]
50 ; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v0, v1, v[2:3]
70 ; CI: v_mad_u64_u32
71 ; CI: v_mad_u64_u32
73 ; CI: v_mad_u64_u32
90 ; SI-NOT: v_mad_u64_u32
114 ; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v0, v2, v[4:5]
158 ; CI: v_mad_u64_u32 v[0:1], s{{\[[0-9]+:[0-9]+\]}}, v1, v0, v[0:1]
159 ; SI-NOT: v_mad_u64_u32
H A Ddag-divergence-atomic.ll19 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, 12, v[0:1]
41 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, 12, v[0:1]
63 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, 12, v[0:1]
85 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, 12, v[0:1]
107 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, 12, v[0:1]
141 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v0, 12, s[2:3]
163 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, 12, v[0:1]
185 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, 12, v[0:1]
207 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, 12, v[0:1]
229 ; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, 12, v[0:1]
[all …]
/dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/AMDGPU/
H A Dmad_64_32.ll35 ; CI: v_mad_u64_u32 v[0:1], s[6:7], v0, v1, v[2:3]
50 ; CI: v_mad_u64_u32 v[0:1], s[6:7], v0, v1, v[2:3]
70 ; CI: v_mad_u64_u32
71 ; CI: v_mad_u64_u32
73 ; CI: v_mad_u64_u32
90 ; SI-NOT: v_mad_u64_u32
114 ; CI: v_mad_u64_u32 v[0:1], s[6:7], v0, v2, v[4:5]
158 ; CI: v_mad_u64_u32 v[0:1], s[6:7], v1, v0, v[0:1]
159 ; SI-NOT: v_mad_u64_u32
/dports/devel/llvm90/llvm-9.0.1.src/test/MC/AMDGPU/
H A Dgfx10-constant-bus.s41 v_mad_u64_u32 v[5:6], s12, v1, 0x12345678, 0x12345678 label
44 v_mad_u64_u32 v[5:6], s12, s1, 0x12345678, 0x12345678 label
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/MC/AMDGPU/
H A Dgfx10-constant-bus.s53 v_mad_u64_u32 v[5:6], s12, v1, 0x12345678, 0x12345678 label
56 v_mad_u64_u32 v[5:6], s12, s1, 0x12345678, 0x12345678 label
/dports/devel/llvm10/llvm-10.0.1.src/test/MC/AMDGPU/
H A Dgfx10-constant-bus.s53 v_mad_u64_u32 v[5:6], s12, v1, 0x12345678, 0x12345678 label
56 v_mad_u64_u32 v[5:6], s12, s1, 0x12345678, 0x12345678 label
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/MC/AMDGPU/
H A Dgfx10-constant-bus.s53 v_mad_u64_u32 v[5:6], s12, v1, 0x12345678, 0x12345678 label
56 v_mad_u64_u32 v[5:6], s12, s1, 0x12345678, 0x12345678 label
/dports/devel/llvm11/llvm-11.0.1.src/test/MC/AMDGPU/
H A Dgfx10-constant-bus.s53 v_mad_u64_u32 v[5:6], s12, v1, 0x12345678, 0x12345678 label
56 v_mad_u64_u32 v[5:6], s12, s1, 0x12345678, 0x12345678 label

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