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/dports/lang/gcc6-aux/gcc-6-20180516/gcc/testsuite/gcc.target/powerpc/
H A Dvec-shift.c14 v16ui vslb(v16ui v, unsigned char i) in vslb() function
/dports/lang/gcc8/gcc-8.5.0/gcc/testsuite/gcc.target/powerpc/
H A Dvec-shift.c14 v16ui vslb(v16ui v, unsigned char i) in vslb() function
/dports/devel/riscv64-none-elf-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/powerpc/
H A Dvec-shift.c14 v16ui vslb(v16ui v, unsigned char i) in vslb() function
/dports/lang/gcc12-devel/gcc-12-20211205/gcc/testsuite/gcc.target/powerpc/
H A Dvec-shift.c13 v16ui vslb(v16ui v, unsigned char i) in vslb() function
/dports/lang/gcc10/gcc-10.3.0/gcc/testsuite/gcc.target/powerpc/
H A Dvec-shift.c13 v16ui vslb(v16ui v, unsigned char i) in vslb() function
/dports/lang/gcc11-devel/gcc-11-20211009/gcc/testsuite/gcc.target/powerpc/
H A Dvec-shift.c13 v16ui vslb(v16ui v, unsigned char i) in vslb() function
/dports/lang/gcc11/gcc-11.2.0/gcc/testsuite/gcc.target/powerpc/
H A Dvec-shift.c13 v16ui vslb(v16ui v, unsigned char i) in vslb() function
/dports/devel/arm-none-eabi-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/powerpc/
H A Dvec-shift.c14 v16ui vslb(v16ui v, unsigned char i) in vslb() function
/dports/devel/riscv32-unknown-elf-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/powerpc/
H A Dvec-shift.c14 v16ui vslb(v16ui v, unsigned char i) in vslb() function
/dports/devel/aarch64-none-elf-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/powerpc/
H A Dvec-shift.c14 v16ui vslb(v16ui v, unsigned char i) in vslb() function
/dports/lang/gcc9-aux/gcc-9.1.0/gcc/testsuite/gcc.target/powerpc/
H A Dvec-shift.c13 v16ui vslb(v16ui v, unsigned char i) in vslb() function
/dports/lang/gcc9-devel/gcc-9-20211007/gcc/testsuite/gcc.target/powerpc/
H A Dvec-shift.c13 v16ui vslb(v16ui v, unsigned char i) in vslb() function
/dports/misc/cxx_atomics_pic/gcc-11.2.0/gcc/testsuite/gcc.target/powerpc/
H A Dvec-shift.c13 v16ui vslb(v16ui v, unsigned char i) in vslb() function
/dports/devel/riscv64-gcc/gcc-8.3.0/gcc/testsuite/gcc.target/powerpc/
H A Dvec-shift.c14 v16ui vslb(v16ui v, unsigned char i) in vslb() function
/dports/devel/avr-gcc/gcc-10.2.0/gcc/testsuite/gcc.target/powerpc/
H A Dvec-shift.c13 v16ui vslb(v16ui v, unsigned char i) in vslb() function
/dports/lang/gnat_util/gcc-6-20180516/gcc/testsuite/gcc.target/powerpc/
H A Dvec-shift.c14 v16ui vslb(v16ui v, unsigned char i) in vslb() function
/dports/lang/gcc9/gcc-9.4.0/gcc/testsuite/gcc.target/powerpc/
H A Dvec-shift.c13 v16ui vslb(v16ui v, unsigned char i) in vslb() function
/dports/lang/gcc10-devel/gcc-10-20211008/gcc/testsuite/gcc.target/powerpc/
H A Dvec-shift.c13 v16ui vslb(v16ui v, unsigned char i) in vslb() function
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/PowerPC/
H A Dmul-const-vector.ll12 ; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]
22 ; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]
33 ; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]
46 ; CHECK-NEXT: vslb v[[REG3:[0-9]+]], v2, v[[REG1]]
58 ; CHECK-NEXT: vslb v[[REG3:[0-9]+]], v2, v[[REG1]]
71 ; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]
84 ; CHECK-NEXT: vslb v[[REG5:[0-9]+]], v2, v[[REG1]]
94 ; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/PowerPC/
H A Dmul-const-vector.ll12 ; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]
22 ; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]
33 ; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]
46 ; CHECK-NEXT: vslb v[[REG3:[0-9]+]], v2, v[[REG1]]
58 ; CHECK-NEXT: vslb v[[REG3:[0-9]+]], v2, v[[REG1]]
71 ; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]
84 ; CHECK-NEXT: vslb v[[REG5:[0-9]+]], v2, v[[REG1]]
94 ; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/PowerPC/
H A Dmul-const-vector.ll12 ; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]
22 ; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]
33 ; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]
46 ; CHECK-NEXT: vslb v[[REG3:[0-9]+]], v2, v[[REG1]]
58 ; CHECK-NEXT: vslb v[[REG3:[0-9]+]], v2, v[[REG1]]
71 ; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]
84 ; CHECK-NEXT: vslb v[[REG5:[0-9]+]], v2, v[[REG1]]
94 ; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/PowerPC/
H A Dmul-const-vector.ll12 ; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]
22 ; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]
33 ; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]
46 ; CHECK-NEXT: vslb v[[REG3:[0-9]+]], v2, v[[REG1]]
58 ; CHECK-NEXT: vslb v[[REG3:[0-9]+]], v2, v[[REG1]]
71 ; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]
84 ; CHECK-NEXT: vslb v[[REG5:[0-9]+]], v2, v[[REG1]]
94 ; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/PowerPC/
H A Dmul-const-vector.ll12 ; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]
22 ; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]
33 ; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]
46 ; CHECK-NEXT: vslb v[[REG3:[0-9]+]], v2, v[[REG1]]
58 ; CHECK-NEXT: vslb v[[REG3:[0-9]+]], v2, v[[REG1]]
71 ; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]
84 ; CHECK-NEXT: vslb v[[REG5:[0-9]+]], v2, v[[REG1]]
94 ; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/PowerPC/
H A Dmul-const-vector.ll12 ; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]
22 ; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]
33 ; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]
46 ; CHECK-NEXT: vslb v[[REG3:[0-9]+]], v2, v[[REG1]]
58 ; CHECK-NEXT: vslb v[[REG3:[0-9]+]], v2, v[[REG1]]
71 ; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]
84 ; CHECK-NEXT: vslb v[[REG5:[0-9]+]], v2, v[[REG1]]
94 ; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/PowerPC/
H A Dmul-const-vector.ll12 ; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]
22 ; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]
33 ; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]
46 ; CHECK-NEXT: vslb v[[REG3:[0-9]+]], v2, v[[REG1]]
58 ; CHECK-NEXT: vslb v[[REG3:[0-9]+]], v2, v[[REG1]]
71 ; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]
84 ; CHECK-NEXT: vslb v[[REG5:[0-9]+]], v2, v[[REG1]]
94 ; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]

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