/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/PowerPC/ |
H A D | mul-const-vector.ll | 189 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 198 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 208 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 220 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 232 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 245 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 259 ; CHECK-NEXT: vslw v[[REG5:[0-9]+]], v2, v[[REG4]] 270 ; CHECK-NEXT: vslw v[[REG5:[0-9]+]], v2, v[[REG4]]
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H A D | sext-vector-inreg.ll | 16 ; CHECK-P8-NEXT: vslw 2, 2, 3
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/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/PowerPC/ |
H A D | mul-const-vector.ll | 189 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 198 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 208 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 220 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 232 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 245 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 259 ; CHECK-NEXT: vslw v[[REG5:[0-9]+]], v2, v[[REG4]] 270 ; CHECK-NEXT: vslw v[[REG5:[0-9]+]], v2, v[[REG4]]
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H A D | sext-vector-inreg.ll | 16 ; CHECK-P8-NEXT: vslw 2, 2, 3
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/PowerPC/ |
H A D | mul-const-vector.ll | 189 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 198 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 208 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 220 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 232 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 245 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 259 ; CHECK-NEXT: vslw v[[REG5:[0-9]+]], v2, v[[REG4]] 270 ; CHECK-NEXT: vslw v[[REG5:[0-9]+]], v2, v[[REG4]]
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H A D | sext-vector-inreg.ll | 16 ; CHECK-P8-NEXT: vslw 2, 2, 3
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/PowerPC/ |
H A D | mul-const-vector.ll | 189 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 198 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 208 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 220 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 232 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 245 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 259 ; CHECK-NEXT: vslw v[[REG5:[0-9]+]], v2, v[[REG4]] 270 ; CHECK-NEXT: vslw v[[REG5:[0-9]+]], v2, v[[REG4]]
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H A D | sext-vector-inreg.ll | 16 ; CHECK-P8-NEXT: vslw 2, 2, 3
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/PowerPC/ |
H A D | mul-const-vector.ll | 189 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 198 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 208 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 220 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 232 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 245 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 259 ; CHECK-NEXT: vslw v[[REG5:[0-9]+]], v2, v[[REG4]] 270 ; CHECK-NEXT: vslw v[[REG5:[0-9]+]], v2, v[[REG4]]
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H A D | sext-vector-inreg.ll | 16 ; CHECK-P8-NEXT: vslw 2, 2, 3
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/PowerPC/ |
H A D | mul-const-vector.ll | 189 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 198 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 208 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 220 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 232 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 245 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 259 ; CHECK-NEXT: vslw v[[REG5:[0-9]+]], v2, v[[REG4]] 270 ; CHECK-NEXT: vslw v[[REG5:[0-9]+]], v2, v[[REG4]]
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H A D | sext-vector-inreg.ll | 16 ; CHECK-P8-NEXT: vslw 2, 2, 3
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/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/PowerPC/ |
H A D | mul-const-vector.ll | 189 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 198 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 208 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 220 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 232 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 245 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 259 ; CHECK-NEXT: vslw v[[REG5:[0-9]+]], v2, v[[REG4]] 270 ; CHECK-NEXT: vslw v[[REG5:[0-9]+]], v2, v[[REG4]]
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H A D | sext-vector-inreg.ll | 16 ; CHECK-P8-NEXT: vslw 2, 2, 3
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/PowerPC/ |
H A D | mul-const-vector.ll | 189 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 198 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 208 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 220 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 232 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 245 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 259 ; CHECK-NEXT: vslw v[[REG5:[0-9]+]], v2, v[[REG4]] 270 ; CHECK-NEXT: vslw v[[REG5:[0-9]+]], v2, v[[REG4]]
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H A D | sext-vector-inreg.ll | 16 ; CHECK-P8-NEXT: vslw 2, 2, 3
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/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/PowerPC/ |
H A D | mul-const-vector.ll | 189 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 198 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 208 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 220 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 232 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 245 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 259 ; CHECK-NEXT: vslw v[[REG5:[0-9]+]], v2, v[[REG4]] 270 ; CHECK-NEXT: vslw v[[REG5:[0-9]+]], v2, v[[REG4]]
|
H A D | funnel-shift-rot.ll | 79 ; CHECK-NEXT: vslw 5, 2, 3 97 ; CHECK-NEXT: vslw 4, 2, 5 172 ; CHECK-NEXT: vslw 2, 2, 3 189 ; CHECK-NEXT: vslw 2, 2, 3
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/PowerPC/ |
H A D | mul-const-vector.ll | 189 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 198 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 208 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 220 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 232 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 245 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 259 ; CHECK-NEXT: vslw v[[REG5:[0-9]+]], v2, v[[REG4]] 270 ; CHECK-NEXT: vslw v[[REG5:[0-9]+]], v2, v[[REG4]]
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/PowerPC/ |
H A D | mul-const-vector.ll | 189 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 198 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 208 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 220 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 232 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 245 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 259 ; CHECK-NEXT: vslw v[[REG5:[0-9]+]], v2, v[[REG4]] 270 ; CHECK-NEXT: vslw v[[REG5:[0-9]+]], v2, v[[REG4]]
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H A D | sext-vector-inreg.ll | 16 ; CHECK-P8-NEXT: vslw 2, 2, 3
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/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/PowerPC/ |
H A D | mul-const-vector.ll | 189 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 198 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 208 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 220 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 232 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 245 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 259 ; CHECK-NEXT: vslw v[[REG5:[0-9]+]], v2, v[[REG4]] 270 ; CHECK-NEXT: vslw v[[REG5:[0-9]+]], v2, v[[REG4]]
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/PowerPC/ |
H A D | mul-const-vector.ll | 189 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 198 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 208 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 220 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 232 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 245 ; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]] 259 ; CHECK-NEXT: vslw v[[REG5:[0-9]+]], v2, v[[REG4]] 270 ; CHECK-NEXT: vslw v[[REG5:[0-9]+]], v2, v[[REG4]]
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/dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/PowerPC/ |
H A D | funnel-shift-rot.ll | 79 ; CHECK-NEXT: vslw 5, 2, 3 97 ; CHECK-NEXT: vslw 4, 2, 5 172 ; CHECK-NEXT: vslw 2, 2, 3 189 ; CHECK-NEXT: vslw 2, 2, 3
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/dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/PowerPC/ |
H A D | funnel-shift-rot.ll | 82 ; CHECK-NEXT: vslw 3, 2, 3 99 ; CHECK-NEXT: vslw 4, 2, 5 178 ; CHECK-NEXT: vslw 2, 2, 4 195 ; CHECK-NEXT: vslw 2, 2, 3
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