Searched refs:ARRAY_MODE (Results 1 – 10 of 10) sorted by relevance
2244 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()2248 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()2252 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()2256 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()2260 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()2264 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()2272 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | in gfx_v8_0_tiling_mode_table_init()2274 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()2416 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()2420 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()[all …]
191 # define ARRAY_MODE(x) ((x) << 2) macro
164 tiling_flags = AMDGPU_TILING_SET(ARRAY_MODE, GRPH_ARRAY_2D_TILED_THIN1); in amdgpufb_create_pinned_object()
1951 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v10_0_crtc_do_set_base()1971 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v10_0_crtc_do_set_base()
1993 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v11_0_crtc_do_set_base()2013 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v11_0_crtc_do_set_base()
2385 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()2389 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()2393 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()2397 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()2401 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()2405 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()2416 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | in cik_tiling_mode_table_init()2418 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()2528 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()2532 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()[all …]
2506 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()2515 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()2524 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()2533 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()2542 tile[4] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in si_tiling_mode_table_init()2551 tile[5] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()2560 tile[6] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()2569 tile[7] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()2578 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | in si_tiling_mode_table_init()2587 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in si_tiling_mode_table_init()[all …]
1180 # define ARRAY_MODE(x) ((x) << 2) macro
1218 # define ARRAY_MODE(x) ((x) << 2) macro
2082 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) { in fill_plane_attributes_from_fb()2101 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) in fill_plane_attributes_from_fb()