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Searched refs:AR_RC (Results 1 – 17 of 17) sorted by relevance

/dragonfly/sys/dev/netif/ath/ath_hal/ar5416/
H A Dar5416_interrupts.c237 OS_REG_WRITE(ah, AR_RC, AR_RC_HOSTIF); in ar5416GetPendingInterrupts()
238 OS_REG_WRITE(ah, AR_RC, 0); in ar5416GetPendingInterrupts()
H A Dar5416_power.c99 OS_REG_WRITE(ah, AR_RC, AR_RC_AHB|AR_RC_HOSTIF); in ar5416SetPowerModeSleep()
H A Dar5416_reset.c1320 OS_REG_WRITE(ah, AR_RC, AR_RC_AHB); in ar5416SetResetPowerOn()
1328 OS_REG_WRITE(ah, AR_RC, 0); in ar5416SetResetPowerOn()
1383 OS_REG_WRITE(ah, AR_RC, AR_RC_AHB|AR_RC_HOSTIF); in ar5416SetReset()
1385 OS_REG_WRITE(ah, AR_RC, AR_RC_AHB); in ar5416SetReset()
1412 OS_REG_WRITE(ah, AR_RC, 0); in ar5416SetReset()
/dragonfly/tools/tools/ath/common/
H A Ddumpregs_5210.c63 DEFBASICfmt(AR_RC, "RC", AR_RC_BITS),
H A Ddumpregs_5211.c222 DEFBASICfmt(AR_RC, "RC", AR_RC_BITS),
H A Ddumpregs_5212.c251 DEFBASIC(AR_RC, "RC"),
H A Ddumpregs_5416.c256 DEFBASICfmt(AR_RC, "RC",
/dragonfly/sys/dev/netif/ath/ath_hal/ar5210/
H A Dar5210_reset.c592 OS_REG_WRITE(ah, AR_RC, resetMask); in ar5210SetResetReg()
598 rt = ath_hal_wait(ah, AR_RC, mask, resetMask); in ar5210SetResetReg()
970 OS_REG_READ(ah, AR_RC)); in ar5210CalNoiseFloor()
H A Dar5210reg.h53 #define AR_RC 0x4000 /* Reset control */ macro
/dragonfly/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_interrupts.c434 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_RC), AR_RC_HOSTIF); in ar9300_get_pending_interrupts()
435 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_RC), 0); in ar9300_get_pending_interrupts()
H A Dar9300_reset.c1681 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_RC), AR_RC_HOSTIF); in ar9300_set_reset()
1686 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_RC), AR_RC_HOSTIF); in ar9300_set_reset()
1852 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_RC), 0); in ar9300_set_reset()
H A Dar9300_attach.c4036 AR_HOSTIF_REG(ah, AR_RC) = in ar9300_init_hostif_offsets()
4151 AR_HOSTIF_REG(ah, AR_RC) = in ar9340_init_hostif_offsets()
H A Dar9300.h726 u_int32_t AR_RC; member
/dragonfly/sys/dev/netif/ath/ath_hal/ar5211/
H A Dar5211reg.h222 #define AR_RC 0x4000 /* Warm reset control register */ macro
H A Dar5211_reset.c757 OS_REG_WRITE(ah, AR_RC, resetMask); in ar5211SetResetReg()
764 rt = ath_hal_wait(ah, AR_RC, mask, resetMask); in ar5211SetResetReg()
/dragonfly/sys/dev/netif/ath/ath_hal/ar5212/
H A Dar5212reg.h231 #define AR_RC 0x4000 /* Warm reset control register */ macro
H A Dar5212_reset.c1273 OS_REG_WRITE(ah, AR_RC, resetMask); in ar5212SetResetReg()
1278 rt = ath_hal_wait(ah, AR_RC, mask, resetMask); in ar5212SetResetReg()