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Searched refs:B0_HWE_IMSK (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/netif/msk/
H A Dif_msk.c1267 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); in mskc_reset()
1268 CSR_READ_4(sc, B0_HWE_IMSK); in mskc_reset()
1809 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); in mskc_detach()
1810 CSR_READ_4(sc, B0_HWE_IMSK); in mskc_detach()
2727 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); in mskc_suspend()
2728 CSR_READ_4(sc, B0_HWE_IMSK); in mskc_suspend()
3101 CSR_WRITE_4(sc, B0_HWE_IMSK, in mskc_intr_hwerr()
3103 CSR_READ_4(sc, B0_HWE_IMSK); in mskc_intr_hwerr()
3581 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); in msk_init()
3582 CSR_READ_4(sc, B0_HWE_IMSK); in msk_init()
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H A Dif_mskreg.h436 #define B0_HWE_IMSK 0x0014 /* 32 bit HW Error Interrupt Mask Reg */ macro