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Searched refs:B0_Y2_SP_ICR (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/netif/msk/
H A Dif_mskreg.h444 #define B0_Y2_SP_ICR 0x002c /* 32 bit Interrupt Control Reg */ macro
H A Dif_msk.c3255 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); in mskc_intr()
3296 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); in mskc_intr()