Searched refs:BANK_HEIGHT (Results 1 – 9 of 9) sorted by relevance
2348 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v8_0_tiling_mode_table_init()2352 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v8_0_tiling_mode_table_init()2356 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v8_0_tiling_mode_table_init()2360 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v8_0_tiling_mode_table_init()2364 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | in gfx_v8_0_tiling_mode_table_init()2368 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v8_0_tiling_mode_table_init()2372 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v8_0_tiling_mode_table_init()2376 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | in gfx_v8_0_tiling_mode_table_init()2380 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v8_0_tiling_mode_table_init()2540 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v8_0_tiling_mode_table_init()[all …]
197 # define BANK_HEIGHT(x) ((x) << 2) macro
1955 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v10_0_crtc_do_set_base()
1997 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v11_0_crtc_do_set_base()
2512 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in si_tiling_mode_table_init()2521 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in si_tiling_mode_table_init()2530 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in si_tiling_mode_table_init()2539 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in si_tiling_mode_table_init()2548 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | in si_tiling_mode_table_init()2557 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | in si_tiling_mode_table_init()2566 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in si_tiling_mode_table_init()2575 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in si_tiling_mode_table_init()2584 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | in si_tiling_mode_table_init()2593 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | in si_tiling_mode_table_init()[all …]
2608 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in cik_tiling_mode_table_init()2612 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | in cik_tiling_mode_table_init()2616 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in cik_tiling_mode_table_init()2620 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in cik_tiling_mode_table_init()2624 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in cik_tiling_mode_table_init()2628 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in cik_tiling_mode_table_init()2632 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in cik_tiling_mode_table_init()2636 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | in cik_tiling_mode_table_init()2640 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in cik_tiling_mode_table_init()2644 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | in cik_tiling_mode_table_init()[all …]
1211 # define BANK_HEIGHT(x) ((x) << 16) macro
1265 # define BANK_HEIGHT(x) ((x) << 2) macro
2086 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in fill_plane_attributes_from_fb()