Searched refs:BANK_WIDTH (Results 1 – 9 of 9) sorted by relevance
2347 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | in gfx_v8_0_tiling_mode_table_init()2351 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | in gfx_v8_0_tiling_mode_table_init()2355 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v8_0_tiling_mode_table_init()2359 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()2363 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()2367 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()2371 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()2375 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | in gfx_v8_0_tiling_mode_table_init()2379 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | in gfx_v8_0_tiling_mode_table_init()2539 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()[all …]
196 # define BANK_WIDTH(x) ((x) << 0) macro
1954 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v10_0_crtc_do_set_base()
1996 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v11_0_crtc_do_set_base()
2511 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()2520 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()2529 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()2538 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()2547 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()2556 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()2565 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()2574 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()2583 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()2592 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()[all …]
2464 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()2468 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()2472 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()2476 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()2480 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()2484 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()2488 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()2492 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()2496 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()2607 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()[all …]
1206 # define BANK_WIDTH(x) ((x) << 14) macro
1260 # define BANK_WIDTH(x) ((x) << 0) macro
2085 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in fill_plane_attributes_from_fb()