Home
last modified time | relevance | path

Searched refs:CNB_PWRMGT_CNTL__FORCE_NB_PS1__SHIFT (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/smu/
H A Dsmu_8_0_sh_mask.h1952 #define CNB_PWRMGT_CNTL__FORCE_NB_PS1__SHIFT 0x3 macro
H A Dsmu_7_0_0_sh_mask.h2976 #define CNB_PWRMGT_CNTL__FORCE_NB_PS1__SHIFT 0x3 macro
H A Dsmu_7_1_1_sh_mask.h3626 #define CNB_PWRMGT_CNTL__FORCE_NB_PS1__SHIFT 0x3 macro
H A Dsmu_7_0_1_sh_mask.h4414 #define CNB_PWRMGT_CNTL__FORCE_NB_PS1__SHIFT 0x3 macro
H A Dsmu_7_1_0_sh_mask.h4606 #define CNB_PWRMGT_CNTL__FORCE_NB_PS1__SHIFT 0x3 macro
H A Dsmu_7_1_2_sh_mask.h4746 #define CNB_PWRMGT_CNTL__FORCE_NB_PS1__SHIFT 0x3 macro
H A Dsmu_7_1_3_sh_mask.h4650 #define CNB_PWRMGT_CNTL__FORCE_NB_PS1__SHIFT 0x3 macro