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Searched refs:CNB_PWRMGT_CNTL__GNB_SLOW_MASK (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/smu/
H A Dsmu_8_0_sh_mask.h1949 #define CNB_PWRMGT_CNTL__GNB_SLOW_MASK 0x4 macro
H A Dsmu_7_0_0_sh_mask.h2973 #define CNB_PWRMGT_CNTL__GNB_SLOW_MASK 0x4 macro
H A Dsmu_7_1_1_sh_mask.h3623 #define CNB_PWRMGT_CNTL__GNB_SLOW_MASK 0x4 macro
H A Dsmu_7_0_1_sh_mask.h4411 #define CNB_PWRMGT_CNTL__GNB_SLOW_MASK 0x4 macro
H A Dsmu_7_1_0_sh_mask.h4603 #define CNB_PWRMGT_CNTL__GNB_SLOW_MASK 0x4 macro
H A Dsmu_7_1_2_sh_mask.h4743 #define CNB_PWRMGT_CNTL__GNB_SLOW_MASK 0x4 macro
H A Dsmu_7_1_3_sh_mask.h4647 #define CNB_PWRMGT_CNTL__GNB_SLOW_MASK 0x4 macro