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Searched refs:CP_RB0_CNTL (Results 1 – 8 of 8) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
H A Dnid.h484 #define CP_RB0_CNTL 0xC104 macro
H A Dsid.h1246 #define CP_RB0_CNTL 0xC104 macro
H A Dcikd.h1302 #define CP_RB0_CNTL 0xC104 macro
H A Dsi.c3660 WREG32(CP_RB0_CNTL, tmp); in si_cp_resume()
3663 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); in si_cp_resume()
3679 WREG32(CP_RB0_CNTL, tmp); in si_cp_resume()
H A Dni.c1641 CP_RB0_CNTL, in cayman_cp_resume()
H A Dcik.c4114 WREG32(CP_RB0_CNTL, tmp); in cik_cp_gfx_resume()
4117 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); in cik_cp_gfx_resume()
4132 WREG32(CP_RB0_CNTL, tmp); in cik_cp_gfx_resume()
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dgfx_v8_0.c4487 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v8_0_cp_gfx_resume()
4488 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v8_0_cp_gfx_resume()
4489 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3); in gfx_v8_0_cp_gfx_resume()
4490 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1); in gfx_v8_0_cp_gfx_resume()
4492 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); in gfx_v8_0_cp_gfx_resume()
H A Dgfx_v9_0.c2468 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v9_0_cp_gfx_resume()
2469 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v9_0_cp_gfx_resume()
2471 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); in gfx_v9_0_cp_gfx_resume()