/dragonfly/sys/dev/netif/xl/ |
H A D | if_xl.c | 349 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 353 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 697 CSR_WRITE_2(sc, XL_W0_EE_CMD, in xl_read_eeprom() 700 CSR_WRITE_2(sc, XL_W0_EE_CMD, in xl_read_eeprom() 2205 CSR_WRITE_2(sc, XL_COMMAND, in xl_txeoc() 2208 CSR_WRITE_2(sc, XL_COMMAND, in xl_txeoc() 2251 CSR_WRITE_2(sc, XL_COMMAND, in xl_npoll_compat() 2327 CSR_WRITE_2(sc, XL_COMMAND, in xl_intr() 2778 CSR_WRITE_2(sc, XL_COMMAND, in xl_init() 3050 CSR_WRITE_2(sc, XL_COMMAND, in xl_ioctl() [all …]
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H A D | if_xlreg.h | 640 #define CSR_WRITE_2(sc, reg, val) \ macro 653 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_WINSEL | x)
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/dragonfly/sys/dev/netif/ste/ |
H A D | if_ste.c | 249 CSR_WRITE_2(sc, STE_PHYCTL, 0); in ste_mii_readreg() 550 CSR_WRITE_2(sc, STE_MAR0, 0); in ste_setmulti() 551 CSR_WRITE_2(sc, STE_MAR1, 0); in ste_setmulti() 552 CSR_WRITE_2(sc, STE_MAR2, 0); in ste_setmulti() 553 CSR_WRITE_2(sc, STE_MAR3, 0); in ste_setmulti() 622 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); in ste_intr() 1199 CSR_WRITE_2(sc, STE_MACCTL0, 0); in ste_init() 1200 CSR_WRITE_2(sc, STE_MACCTL1, 0); in ste_init() 1208 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); in ste_init() 1209 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); in ste_init() [all …]
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/dragonfly/sys/dev/netif/wi/ |
H A D | if_wi_pci.c | 172 CSR_WRITE_2(sc, WI_INT_EN, 0); in wi_pci_attach() 173 CSR_WRITE_2(sc, WI_EVENT_ACK, 0xFFFF); in wi_pci_attach() 220 CSR_WRITE_2(sc, WI_PCICOR_OFF, WI_PCICOR_RESET); in wi_pci_attach() 223 CSR_WRITE_2(sc, WI_PCICOR_OFF, 0x0000); in wi_pci_attach() 238 CSR_WRITE_2(sc, WI_HFA384X_SWSUPPORT0_OFF, WI_PRISM2STA_MAGIC); in wi_pci_attach()
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H A D | if_wi.c | 604 CSR_WRITE_2(sc, WI_INT_EN, 0); in wi_intr() 611 CSR_WRITE_2(sc, WI_INT_EN, 0); in wi_intr() 626 CSR_WRITE_2(sc, WI_INT_EN, WI_INTRS); in wi_intr() 712 CSR_WRITE_2(sc, WI_INT_EN, 0); in wi_stop() 1139 CSR_WRITE_2(sc, WI_INT_EN, 0); in wi_reset() 1831 CSR_WRITE_2(sc, WI_PARAM0, val0); in wi_cmd() 1832 CSR_WRITE_2(sc, WI_PARAM1, val1); in wi_cmd() 1833 CSR_WRITE_2(sc, WI_PARAM2, val2); in wi_cmd() 1834 CSR_WRITE_2(sc, WI_COMMAND, cmd); in wi_cmd() 1873 CSR_WRITE_2(sc, WI_SEL0, id); in wi_seek_bap() [all …]
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H A D | if_wi_pccard.c | 221 CSR_WRITE_2(sc, WI_INT_EN, 0); in wi_pccard_attach() 222 CSR_WRITE_2(sc, WI_EVENT_ACK, 0xFFFF); in wi_pccard_attach()
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/dragonfly/sys/dev/netif/stge/ |
H A D | if_stge.c | 540 CSR_WRITE_2(sc, STGE_EepromCtrl, in stge_read_eeprom() 1732 CSR_WRITE_2(sc, STGE_IntEnable, 0); in stge_npoll() 1964 CSR_WRITE_2(sc, STGE_RxEarlyThresh, 0x7ff); in stge_init() 1989 CSR_WRITE_2(sc, STGE_IntEnable, 0); in stge_init() 2029 CSR_WRITE_2(sc, STGE_DebugCtrl, in stge_init() 2033 CSR_WRITE_2(sc, STGE_DebugCtrl, in stge_init() 2036 CSR_WRITE_2(sc, STGE_DebugCtrl, in stge_init() 2120 CSR_WRITE_2(sc, STGE_IntEnable, 0); in stge_stop() 2388 CSR_WRITE_2(sc, STGE_ReceiveMode, mode); in stge_set_filter() 2407 CSR_WRITE_2(sc, STGE_ReceiveMode, mode); in stge_set_multi() [all …]
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/dragonfly/sys/dev/netif/fxp/ |
H A D | if_fxp.c | 874 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); in fxp_eeprom_shiftin() 878 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); in fxp_eeprom_shiftin() 896 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); in fxp_eeprom_getword() 910 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); in fxp_eeprom_getword() 914 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); in fxp_eeprom_getword() 933 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); in fxp_eeprom_getword() 936 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); in fxp_eeprom_getword() 953 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); in fxp_eeprom_putword() 962 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); in fxp_eeprom_putword() 974 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); in fxp_eeprom_putword() [all …]
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H A D | if_fxpvar.h | 153 #define CSR_WRITE_2(sc, reg, val) \ macro
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/dragonfly/sys/dev/netif/vge/ |
H A D | if_vgevar.h | 138 #define CSR_WRITE_2(sc, reg, val) \ macro 153 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x)) 160 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
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H A D | if_vge.c | 403 CSR_WRITE_2(sc, VGE_MIIDATA, data); in vge_miibus_writereg() 1408 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim); in vge_rxeof() 1746 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); in vge_start() 1822 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1); in vge_init() 1826 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1); in vge_init() 1827 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT); in vge_init() 1834 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); in vge_init() 1874 CSR_WRITE_2(sc, VGE_SSTIMER, 400); in vge_init() 2098 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); in vge_stop()
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/dragonfly/sys/dev/netif/tl/ |
H A D | if_tl.c | 362 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); in tl_dio_read8() 369 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); in tl_dio_read16() 376 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); in tl_dio_read32() 383 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); in tl_dio_write8() 391 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); in tl_dio_write16() 399 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); in tl_dio_write32() 409 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); in tl_dio_setbit() 422 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); in tl_dio_clrbit() 435 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); in tl_dio_setbit16() 448 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); in tl_dio_clrbit16() [all …]
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/dragonfly/sys/dev/netif/msk/ |
H A D | if_msk.c | 622 CSR_WRITE_2(sc_if->msk_softc, in msk_init_rx_ring() 661 CSR_WRITE_2(sc_if->msk_softc, in msk_init_jumbo_rx_ring() 1147 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); in mskc_reset() 1148 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); in mskc_reset() 1158 CSR_WRITE_2(sc, B0_CTST, CS_MRST_CLR); in mskc_reset() 1317 CSR_WRITE_2(sc, STAT_TX_IDX_TH, 0x0a); in mskc_reset() 1575 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); in mskc_attach() 1816 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); in mskc_detach() 2639 CSR_WRITE_2(sc_if->msk_softc, in msk_start() 2704 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); in mskc_shutdown() [all …]
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/dragonfly/sys/dev/netif/vr/ |
H A D | if_vr.c | 217 CSR_WRITE_2(sc, reg, \ 221 CSR_WRITE_2(sc, reg, \ 435 CSR_WRITE_2(sc, VR_MIIDATA, frame->mii_data); 1200 CSR_WRITE_2(sc, VR_IMR, 0x0000); in vr_intr() 1205 CSR_WRITE_2(sc, VR_ISR, status); in vr_intr() 1259 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); in vr_intr() 1476 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); in vr_init() 1480 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); in vr_init() 1584 CSR_WRITE_2(sc, VR_IMR, 0x0000); in vr_npoll() 1590 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); in vr_npoll() [all …]
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/dragonfly/sys/dev/netif/rl/ |
H A D | if_rl.c | 413 CSR_WRITE_2(sc, RL_MII, 0); in rl_mii_readreg() 616 CSR_WRITE_2(sc, rl8139_reg, data); in rl_miibus_writereg() 1091 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); in rl_rxeof() 1196 CSR_WRITE_2(sc, RL_ISR, status); in rl_npoll_compat() 1225 CSR_WRITE_2(sc, RL_IMR, 0x0000); in rl_npoll() 1232 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); in rl_npoll() 1261 CSR_WRITE_2(sc, RL_ISR, status); in rl_intr() 1464 CSR_WRITE_2(sc, RL_IMR, 0); in rl_init() 1471 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); in rl_init() 1591 CSR_WRITE_2(sc, RL_IMR, 0x0000); in rl_stop()
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/dragonfly/sys/dev/netif/tx/ |
H A D | if_txvar.h | 108 #define CSR_WRITE_2(sc, reg, val) \ macro
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/dragonfly/sys/dev/netif/iwi/ |
H A D | if_iwireg.h | 587 #define CSR_WRITE_2(sc, reg, val) \ macro 607 CSR_WRITE_2((sc), IWI_CSR_INDIRECT_DATA, (val)); \
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/dragonfly/sys/dev/netif/sk/ |
H A D | if_sk.c | 333 CSR_WRITE_2(sc, reg, x); in sk_win_write_2() 1052 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); in sk_reset() 1053 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); in sk_reset() 1055 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); in sk_reset() 1058 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); in sk_reset() 1060 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); in sk_reset() 1062 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); in sk_reset() 1503 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); in skc_attach() 1771 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); in skc_shutdown()
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/dragonfly/sys/dev/netif/ale/ |
H A D | if_alevar.h | 231 #define CSR_WRITE_2(_sc, reg, val) \ macro
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/dragonfly/sys/dev/netif/age/ |
H A D | if_agevar.h | 231 #define CSR_WRITE_2(_sc, reg, val) \ macro
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/dragonfly/sys/dev/netif/alc/ |
H A D | if_alcvar.h | 262 #define CSR_WRITE_2(sc, reg, val) \ macro
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/dragonfly/sys/dev/netif/re/ |
H A D | if_revar.h | 225 #define CSR_WRITE_2(sc, reg, val) \ macro
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H A D | if_re.c | 849 CSR_WRITE_2(sc, RE_RxMaxSize, sc->re_rxbuf_size); in re_attach() 2280 CSR_WRITE_2(sc, RE_IM, in re_setup_hw_im() 2290 CSR_WRITE_2(sc, RE_IM, 0); in re_disable_hw_im() 2545 CSR_WRITE_2(sc, RE_IMR, val); in re_write_imr() 2551 CSR_WRITE_2(sc, RE_ISR, val); in re_write_isr() 2563 CSR_WRITE_2(sc, RE_TPPOLL_8125, RE_NPQ_8125); in re_start_xmit_8125()
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/dragonfly/sys/dev/netif/pcn/ |
H A D | if_pcnreg.h | 452 #define CSR_WRITE_2(sc, reg, val) \ macro
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/dragonfly/sys/dev/netif/wb/ |
H A D | if_wbreg.h | 388 #define CSR_WRITE_2(sc, reg, val) \ macro
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