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Searched refs:D1VGA_CONTROL (Results 1 – 8 of 8) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
H A Davivod.h44 #define D1VGA_CONTROL 0x0330 macro
/dragonfly/sys/dev/drm/amd/display/dc/dce120/
H A Ddce120_timing_generator.c433 set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_MODE_ENABLE); in dce120_timing_generator_disable_vga()
434 set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_TIMING_SELECT); in dce120_timing_generator_disable_vga()
436 value, 0, D1VGA_CONTROL, D1VGA_SYNC_POLARITY_SELECT); in dce120_timing_generator_disable_vga()
437 set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_OVERSCAN_COLOR_EN); in dce120_timing_generator_disable_vga()
/dragonfly/sys/dev/drm/amd/display/dc/dce/
H A Ddce_hwseq.h190 SR(D1VGA_CONTROL), \
261 uint32_t D1VGA_CONTROL; member
413 HWS_SF(, D1VGA_CONTROL, D1VGA_MODE_ENABLE, mask_sh),\
/dragonfly/sys/dev/drm/amd/display/dc/dce110/
H A Ddce110_timing_generator.c1829 set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_MODE_ENABLE); in dce110_timing_generator_disable_vga()
1830 set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_TIMING_SELECT); in dce110_timing_generator_disable_vga()
1832 value, 0, D1VGA_CONTROL, D1VGA_SYNC_POLARITY_SELECT); in dce110_timing_generator_disable_vga()
1833 set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_OVERSCAN_COLOR_EN); in dce110_timing_generator_disable_vga()
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dgmc_v9_0.c812 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { in gmc_v9_0_get_vbios_fb_size()
H A Dgmc_v7_0.c961 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { in gmc_v7_0_get_vbios_fb_size()
H A Dgmc_v8_0.c1079 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { in gmc_v8_0_get_vbios_fb_size()
/dragonfly/sys/dev/drm/amd/display/dc/dcn10/
H A Ddcn10_hw_sequencer.c387 REG_GET(D1VGA_CONTROL, D1VGA_MODE_ENABLE, &in_vga1_mode); in disable_vga()
396 REG_WRITE(D1VGA_CONTROL, 0); in disable_vga()