Searched refs:D1VGA_CONTROL (Results 1 – 8 of 8) sorted by relevance
/dragonfly/sys/dev/drm/radeon/ |
H A D | avivod.h | 44 #define D1VGA_CONTROL 0x0330 macro
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/dragonfly/sys/dev/drm/amd/display/dc/dce120/ |
H A D | dce120_timing_generator.c | 433 set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_MODE_ENABLE); in dce120_timing_generator_disable_vga() 434 set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_TIMING_SELECT); in dce120_timing_generator_disable_vga() 436 value, 0, D1VGA_CONTROL, D1VGA_SYNC_POLARITY_SELECT); in dce120_timing_generator_disable_vga() 437 set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_OVERSCAN_COLOR_EN); in dce120_timing_generator_disable_vga()
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/dragonfly/sys/dev/drm/amd/display/dc/dce/ |
H A D | dce_hwseq.h | 190 SR(D1VGA_CONTROL), \ 261 uint32_t D1VGA_CONTROL; member 413 HWS_SF(, D1VGA_CONTROL, D1VGA_MODE_ENABLE, mask_sh),\
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/dragonfly/sys/dev/drm/amd/display/dc/dce110/ |
H A D | dce110_timing_generator.c | 1829 set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_MODE_ENABLE); in dce110_timing_generator_disable_vga() 1830 set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_TIMING_SELECT); in dce110_timing_generator_disable_vga() 1832 value, 0, D1VGA_CONTROL, D1VGA_SYNC_POLARITY_SELECT); in dce110_timing_generator_disable_vga() 1833 set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_OVERSCAN_COLOR_EN); in dce110_timing_generator_disable_vga()
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/dragonfly/sys/dev/drm/amd/amdgpu/ |
H A D | gmc_v9_0.c | 812 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { in gmc_v9_0_get_vbios_fb_size()
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H A D | gmc_v7_0.c | 961 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { in gmc_v7_0_get_vbios_fb_size()
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H A D | gmc_v8_0.c | 1079 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { in gmc_v8_0_get_vbios_fb_size()
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/dragonfly/sys/dev/drm/amd/display/dc/dcn10/ |
H A D | dcn10_hw_sequencer.c | 387 REG_GET(D1VGA_CONTROL, D1VGA_MODE_ENABLE, &in_vga1_mode); in disable_vga() 396 REG_WRITE(D1VGA_CONTROL, 0); in disable_vga()
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