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Searched refs:D3VGA_CONTROL (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/drm/amd/display/dc/dce/
H A Ddce_hwseq.h192 SR(D3VGA_CONTROL), \
263 uint32_t D3VGA_CONTROL; member
415 HWS_SF(, D3VGA_CONTROL, D3VGA_MODE_ENABLE, mask_sh),\
/dragonfly/sys/dev/drm/amd/display/dc/dcn10/
H A Ddcn10_hw_sequencer.c389 REG_GET(D3VGA_CONTROL, D3VGA_MODE_ENABLE, &in_vga3_mode); in disable_vga()
398 REG_WRITE(D3VGA_CONTROL, 0); in disable_vga()