Searched refs:DCE3_HDMI_OFFSET1 (Results 1 – 3 of 3) sorted by relevance
178 #define DCE3_HDMI_OFFSET1 (0x7800 - 0x7400) macro
3661 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; in r600_disable_interrupt_state()3662 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); in r600_disable_interrupt_state()3806 hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK; in r600_irq_set()3902 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1); in r600_irq_set()3936 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1); in r600_irq_ack()4018 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1); in r600_irq_ack()4020 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); in r600_irq_ack()
1564 rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1; in radeon_afmt_init()