Searched refs:DCFCLK_CNTL (Results 1 – 2 of 2) sorted by relevance
/dragonfly/sys/dev/drm/amd/display/dc/dce/ |
H A D | dce_hwseq.h | 148 SR(DCFCLK_CNTL),\ 149 SR(DCFCLK_CNTL), \ 247 uint32_t DCFCLK_CNTL; member 367 HWS_SF(, DCFCLK_CNTL, DCFCLK_GATE_DIS, mask_sh), \
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/dragonfly/sys/dev/drm/amd/display/dc/dcn10/ |
H A D | dcn10_hw_sequencer.c | 975 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); in dcn10_init_hw() 1092 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); in dcn10_init_hw()
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