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Searched refs:DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL__SHIFT (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h4752 #define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL__SHIFT 0x00000008 macro
H A Ddce_8_0_sh_mask.h3296 #define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL__SHIFT 0x8 macro
H A Ddce_10_0_sh_mask.h3218 #define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL__SHIFT 0x8 macro
H A Ddce_11_0_sh_mask.h3288 #define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL__SHIFT 0x8 macro
H A Ddce_11_2_sh_mask.h3536 #define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL__SHIFT 0x8 macro
H A Ddce_12_0_sh_mask.h9372 #define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL__SHIFT … macro