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Searched refs:DCI_MEM_PWR_STATE__DMIF5_MEM_PWR_STATE_MASK (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h4645 #define DCI_MEM_PWR_STATE__DMIF5_MEM_PWR_STATE_MASK 0x00003000L macro
H A Ddce_8_0_sh_mask.h2511 #define DCI_MEM_PWR_STATE__DMIF5_MEM_PWR_STATE_MASK 0x3000 macro