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Searched refs:DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h3462 #define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT 0x00000014 macro
H A Ddce_8_0_sh_mask.h3868 #define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT 0x14 macro
H A Ddce_10_0_sh_mask.h3772 #define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT 0x14 macro
H A Ddce_11_0_sh_mask.h3860 #define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT 0x14 macro
H A Ddce_11_2_sh_mask.h4242 #define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT 0x14 macro
H A Ddce_12_0_sh_mask.h10226 #define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_sh_mask.h40836 #define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT … macro