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Searched refs:DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT_MASK (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h5623 #define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT_MASK 0x04000000L macro
H A Ddce_8_0_sh_mask.h6925 #define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT_MASK 0x4000000 macro
H A Ddce_10_0_sh_mask.h14922 #define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT_MASK 0x4000000 macro
H A Ddce_11_0_sh_mask.h15068 #define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT_MASK 0x4000000 macro
H A Ddce_11_2_sh_mask.h15732 #define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT_MASK 0x4000000 macro
H A Ddce_12_0_sh_mask.h8010 #define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT_MASK … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_sh_mask.h4984 #define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT_MASK … macro