Searched refs:DMA_CNTL (Results 1 – 9 of 9) sorted by relevance
/dragonfly/sys/dev/drm/radeon/ |
H A D | r600_dma.c | 158 dma_cntl = RREG32(DMA_CNTL); in r600_dma_resume() 160 WREG32(DMA_CNTL, dma_cntl); in r600_dma_resume()
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H A D | ni_dma.c | 237 dma_cntl = RREG32(DMA_CNTL + reg_offset); in cayman_dma_resume() 239 WREG32(DMA_CNTL + reg_offset, dma_cntl); in cayman_dma_resume()
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H A D | si.c | 5944 tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_disable_interrupt_state() 5945 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, tmp); in si_disable_interrupt_state() 5946 tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_disable_interrupt_state() 5947 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp); in si_disable_interrupt_state() 6060 dma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_irq_set() 6061 dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_irq_set() 6093 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, dma_cntl); in si_irq_set() 6094 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, dma_cntl1); in si_irq_set()
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H A D | nid.h | 1323 #define DMA_CNTL 0xd02c macro
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H A D | r600.c | 3637 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; in r600_disable_interrupt_state() 3638 WREG32(DMA_CNTL, tmp); in r600_disable_interrupt_state() 3819 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE; in r600_irq_set() 3888 WREG32(DMA_CNTL, dma_cntl); in r600_irq_set()
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H A D | evergreen.c | 4453 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; in evergreen_disable_interrupt_state() 4454 WREG32(DMA_CNTL, tmp); in evergreen_disable_interrupt_state() 4500 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE; in evergreen_irq_set() 4549 WREG32(DMA_CNTL, dma_cntl); in evergreen_irq_set()
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H A D | sid.h | 1833 #define DMA_CNTL 0xd02c macro
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H A D | evergreend.h | 1404 #define DMA_CNTL 0xd02c macro
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H A D | r600d.h | 631 #define DMA_CNTL 0xd02c macro
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