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Searched refs:DMA_CNTL (Results 1 – 9 of 9) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
H A Dr600_dma.c158 dma_cntl = RREG32(DMA_CNTL); in r600_dma_resume()
160 WREG32(DMA_CNTL, dma_cntl); in r600_dma_resume()
H A Dni_dma.c237 dma_cntl = RREG32(DMA_CNTL + reg_offset); in cayman_dma_resume()
239 WREG32(DMA_CNTL + reg_offset, dma_cntl); in cayman_dma_resume()
H A Dsi.c5944 tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_disable_interrupt_state()
5945 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, tmp); in si_disable_interrupt_state()
5946 tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_disable_interrupt_state()
5947 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp); in si_disable_interrupt_state()
6060 dma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_irq_set()
6061 dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_irq_set()
6093 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, dma_cntl); in si_irq_set()
6094 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, dma_cntl1); in si_irq_set()
H A Dnid.h1323 #define DMA_CNTL 0xd02c macro
H A Dr600.c3637 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; in r600_disable_interrupt_state()
3638 WREG32(DMA_CNTL, tmp); in r600_disable_interrupt_state()
3819 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE; in r600_irq_set()
3888 WREG32(DMA_CNTL, dma_cntl); in r600_irq_set()
H A Devergreen.c4453 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; in evergreen_disable_interrupt_state()
4454 WREG32(DMA_CNTL, tmp); in evergreen_disable_interrupt_state()
4500 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE; in evergreen_irq_set()
4549 WREG32(DMA_CNTL, dma_cntl); in evergreen_irq_set()
H A Dsid.h1833 #define DMA_CNTL 0xd02c macro
H A Devergreend.h1404 #define DMA_CNTL 0xd02c macro
H A Dr600d.h631 #define DMA_CNTL 0xd02c macro