Searched refs:DMA_RB_CNTL (Results 1 – 10 of 10) sorted by relevance
/dragonfly/sys/dev/drm/radeon/ |
H A D | ni_dma.c | 164 rb_cntl = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in cayman_dma_stop() 166 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, rb_cntl); in cayman_dma_stop() 169 rb_cntl = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in cayman_dma_stop() 171 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, rb_cntl); in cayman_dma_stop() 213 WREG32(DMA_RB_CNTL + reg_offset, rb_cntl); in cayman_dma_resume() 244 WREG32(DMA_RB_CNTL + reg_offset, rb_cntl | DMA_RB_ENABLE); in cayman_dma_resume()
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H A D | r600_dma.c | 99 u32 rb_cntl = RREG32(DMA_RB_CNTL); in r600_dma_stop() 105 WREG32(DMA_RB_CNTL, rb_cntl); in r600_dma_stop() 134 WREG32(DMA_RB_CNTL, rb_cntl); in r600_dma_resume() 168 WREG32(DMA_RB_CNTL, rb_cntl | DMA_RB_ENABLE); in r600_dma_resume()
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H A D | ni.c | 1859 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in cayman_gpu_soft_reset() 1861 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); in cayman_gpu_soft_reset() 1866 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in cayman_gpu_soft_reset() 1868 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); in cayman_gpu_soft_reset()
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H A D | si.c | 3870 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in si_gpu_soft_reset() 3872 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); in si_gpu_soft_reset() 3876 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in si_gpu_soft_reset() 3878 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); in si_gpu_soft_reset() 4037 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in si_gpu_pci_config_reset() 4039 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); in si_gpu_pci_config_reset() 4041 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in si_gpu_pci_config_reset() 4043 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); in si_gpu_pci_config_reset()
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H A D | nid.h | 1304 #define DMA_RB_CNTL 0xd000 macro
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H A D | r600.c | 1699 tmp = RREG32(DMA_RB_CNTL); in r600_gpu_soft_reset() 1701 WREG32(DMA_RB_CNTL, tmp); in r600_gpu_soft_reset() 1830 tmp = RREG32(DMA_RB_CNTL); in r600_gpu_pci_config_reset() 1832 WREG32(DMA_RB_CNTL, tmp); in r600_gpu_pci_config_reset()
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H A D | evergreen.c | 3894 tmp = RREG32(DMA_RB_CNTL); in evergreen_gpu_soft_reset() 3896 WREG32(DMA_RB_CNTL, tmp); in evergreen_gpu_soft_reset() 4003 tmp = RREG32(DMA_RB_CNTL); in evergreen_gpu_pci_config_reset() 4005 WREG32(DMA_RB_CNTL, tmp); in evergreen_gpu_pci_config_reset()
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H A D | sid.h | 1815 #define DMA_RB_CNTL 0xd000 macro
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H A D | evergreend.h | 2618 #define DMA_RB_CNTL 0xd000 macro
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H A D | r600d.h | 613 #define DMA_RB_CNTL 0xd000 macro
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