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Searched refs:DMA_RB_CNTL (Results 1 – 10 of 10) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
H A Dni_dma.c164 rb_cntl = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in cayman_dma_stop()
166 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, rb_cntl); in cayman_dma_stop()
169 rb_cntl = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in cayman_dma_stop()
171 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, rb_cntl); in cayman_dma_stop()
213 WREG32(DMA_RB_CNTL + reg_offset, rb_cntl); in cayman_dma_resume()
244 WREG32(DMA_RB_CNTL + reg_offset, rb_cntl | DMA_RB_ENABLE); in cayman_dma_resume()
H A Dr600_dma.c99 u32 rb_cntl = RREG32(DMA_RB_CNTL); in r600_dma_stop()
105 WREG32(DMA_RB_CNTL, rb_cntl); in r600_dma_stop()
134 WREG32(DMA_RB_CNTL, rb_cntl); in r600_dma_resume()
168 WREG32(DMA_RB_CNTL, rb_cntl | DMA_RB_ENABLE); in r600_dma_resume()
H A Dni.c1859 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in cayman_gpu_soft_reset()
1861 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); in cayman_gpu_soft_reset()
1866 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in cayman_gpu_soft_reset()
1868 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); in cayman_gpu_soft_reset()
H A Dsi.c3870 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in si_gpu_soft_reset()
3872 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); in si_gpu_soft_reset()
3876 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in si_gpu_soft_reset()
3878 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); in si_gpu_soft_reset()
4037 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in si_gpu_pci_config_reset()
4039 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); in si_gpu_pci_config_reset()
4041 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in si_gpu_pci_config_reset()
4043 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); in si_gpu_pci_config_reset()
H A Dnid.h1304 #define DMA_RB_CNTL 0xd000 macro
H A Dr600.c1699 tmp = RREG32(DMA_RB_CNTL); in r600_gpu_soft_reset()
1701 WREG32(DMA_RB_CNTL, tmp); in r600_gpu_soft_reset()
1830 tmp = RREG32(DMA_RB_CNTL); in r600_gpu_pci_config_reset()
1832 WREG32(DMA_RB_CNTL, tmp); in r600_gpu_pci_config_reset()
H A Devergreen.c3894 tmp = RREG32(DMA_RB_CNTL); in evergreen_gpu_soft_reset()
3896 WREG32(DMA_RB_CNTL, tmp); in evergreen_gpu_soft_reset()
4003 tmp = RREG32(DMA_RB_CNTL); in evergreen_gpu_pci_config_reset()
4005 WREG32(DMA_RB_CNTL, tmp); in evergreen_gpu_pci_config_reset()
H A Dsid.h1815 #define DMA_RB_CNTL 0xd000 macro
H A Devergreend.h2618 #define DMA_RB_CNTL 0xd000 macro
H A Dr600d.h613 #define DMA_RB_CNTL 0xd000 macro