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Searched refs:DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h5797 #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK 0x04000000L macro
H A Ddce_8_0_sh_mask.h7959 #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK 0x4000000 macro
H A Ddce_10_0_sh_mask.h6987 #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK 0x4000000 macro
H A Ddce_11_0_sh_mask.h6889 #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK 0x4000000 macro
H A Ddce_11_2_sh_mask.h7961 #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK 0x4000000 macro
H A Ddce_12_0_sh_mask.h4914 #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_sh_mask.h3876 #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK … macro