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Searched refs:DPLL_CTRL1_LINK_RATE_810 (Results 1 – 4 of 4) sorted by relevance

/dragonfly/sys/dev/drm/i915/
H A Dintel_cdclk.c775 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0): in skl_dpll0_update()
885 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, in skl_dpll0_enable()
H A Dintel_dpll_mgr.c1337 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0); in skl_ddi_dp_set_dpll_hw_state()
H A Dintel_ddi.c1374 case DPLL_CTRL1_LINK_RATE_810: in skl_ddi_clock_get()
H A Di915_reg.h8548 #define DPLL_CTRL1_LINK_RATE_810 2 macro