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Searched refs:DPMTABLE_OD_UPDATE_MCLK (Results 1 – 11 of 11) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
H A Dci_dpm.h189 #define DPMTABLE_OD_UPDATE_MCLK 0x00000002 macro
H A Dci_dpm.c1504 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { in ci_unfreeze_sclk_mclk_dpm()
1612 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { in ci_freeze_sclk_mclk_dpm()
3921 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; in ci_find_dpm_states_clocks_in_dpm_table()
3944 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) in ci_populate_and_upload_sclk_mclk_dpm_levels()
3953 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) { in ci_populate_and_upload_sclk_mclk_dpm_levels()
4804 if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) in ci_update_and_upload_mc_reg_table()
/dragonfly/sys/dev/drm/amd/powerplay/hwmgr/
H A Dvega12_hwmgr.h176 #define DPMTABLE_OD_UPDATE_MCLK 0x00000002 macro
H A Dsmu7_hwmgr.c915 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; in smu7_check_dpm_table_updated()
925 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_MCLK; in smu7_check_dpm_table_updated()
940 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK; in smu7_check_dpm_table_updated()
3629 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; in smu7_find_dpm_states_clocks_in_dpm_table()
3731 DPMTABLE_OD_UPDATE_MCLK)) { in smu7_freeze_sclk_mclk_dpm()
3765 if (hwmgr->od_enabled && data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) { in smu7_populate_and_upload_sclk_mclk_dpm_levels()
3781 (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) { in smu7_populate_and_upload_sclk_mclk_dpm_levels()
3884 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { in smu7_unfreeze_sclk_mclk_dpm()
4222 DPMTABLE_OD_UPDATE_MCLK | in smu7_check_states_equal()
H A Dvega10_hwmgr.c1741 if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_MCLK) { in vega10_populate_single_memory_level()
2434 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_MCLK; in vega10_check_dpm_table_updated()
2450 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK; in vega10_check_dpm_table_updated()
2480 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK; in vega10_init_smc_table()
3280 if (hwmgr->od_enabled && data->need_update_dpm_table & DPMTABLE_OD_UPDATE_MCLK) { in vega10_populate_and_upload_sclk_mclk_dpm_levels()
3294 (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) { in vega10_populate_and_upload_sclk_mclk_dpm_levels()
4836 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; in vega10_odn_edit_dpm_table()
/dragonfly/sys/dev/drm/amd/powerplay/inc/
H A Dhardwaremanager.h376 #define DPMTABLE_OD_UPDATE_MCLK 0x00000002 macro
/dragonfly/sys/dev/drm/amd/powerplay/smumgr/
H A Diceland_smumgr.c1781 if (0 == (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) in iceland_update_and_upload_mc_reg_table()
2168 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK)) in iceland_program_mem_timing_parameters()
H A Dci_smumgr.c1814 if (0 == (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) in ci_update_and_upload_mc_reg_table()
2202 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK)) in ci_program_mem_timing_parameters()
H A Dtonga_smumgr.c2151 if (0 == (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) in tonga_update_and_upload_mc_reg_table()
2547 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK)) in tonga_program_mem_timing_parameters()
H A Dfiji_smumgr.c2267 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK)) in fiji_program_mem_timing_parameters()
H A Dpolaris10_smumgr.c1982 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK)) in polaris10_program_mem_timing_parameters()