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Searched refs:DSPCLK_GATE_D (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/i915/
H A Dintel_i2c.c139 val = I915_READ(DSPCLK_GATE_D); in intel_i2c_quirk_set()
144 I915_WRITE(DSPCLK_GATE_D, val); in intel_i2c_quirk_set()
H A Dintel_dsi.c828 val = I915_READ(DSPCLK_GATE_D); in intel_dsi_pre_enable()
830 I915_WRITE(DSPCLK_GATE_D, val); in intel_dsi_pre_enable()
984 val = I915_READ(DSPCLK_GATE_D); in intel_dsi_post_disable()
986 I915_WRITE(DSPCLK_GATE_D, val); in intel_dsi_post_disable()
H A Dintel_overlay.c198 I915_WRITE(DSPCLK_GATE_D, 0); in i830_overlay_clock_gating()
200 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); in i830_overlay_clock_gating()
H A Dintel_runtime_pm.c880 val = I915_READ(DSPCLK_GATE_D); in vlv_init_display_clock_gating()
883 I915_WRITE(DSPCLK_GATE_D, val); in vlv_init_display_clock_gating()
H A Dintel_pm.c8907 I915_WRITE(DSPCLK_GATE_D, dspclk_gate); in g4x_init_clock_gating()
8923 I915_WRITE(DSPCLK_GATE_D, 0); in i965gm_init_clock_gating()
H A Di915_reg.h3236 #define DSPCLK_GATE_D _MMIO(dev_priv->info.display_mmio_offset + 0x6200) macro