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Searched refs:DVOACLKC_MVP_CNTL__MVP_CLK_B_SRC_SEL__SHIFT (Results 1 – 4 of 4) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h6660 #define DVOACLKC_MVP_CNTL__MVP_CLK_B_SRC_SEL__SHIFT 0x0000001c macro
H A Ddce_8_0_sh_mask.h1976 #define DVOACLKC_MVP_CNTL__MVP_CLK_B_SRC_SEL__SHIFT 0x1c macro
H A Ddce_10_0_sh_mask.h1864 #define DVOACLKC_MVP_CNTL__MVP_CLK_B_SRC_SEL__SHIFT 0x1c macro
H A Ddce_12_0_sh_mask.h3055 #define DVOACLKC_MVP_CNTL__MVP_CLK_B_SRC_SEL__SHIFT macro