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Searched refs:EVERGREEN_CRTC4_REGISTER_OFFSET (Results 1 – 9 of 9) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
H A Devergreen_reg.h228 #define EVERGREEN_CRTC4_REGISTER_OFFSET (0x11df0 - 0x6df0) macro
H A Dradeon_display.c1526 EVERGREEN_CRTC4_REGISTER_OFFSET, in radeon_afmt_init()
1878 EVERGREEN_CRTC4_REGISTER_OFFSET); in radeon_get_crtc_scanoutpos()
1880 EVERGREEN_CRTC4_REGISTER_OFFSET); in radeon_get_crtc_scanoutpos()
H A Dcik.c6936 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
6949 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
7219 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5); in cik_irq_set()
7236 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, in cik_irq_set()
7288 EVERGREEN_CRTC4_REGISTER_OFFSET); in cik_irq_ack()
7327 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, in cik_irq_ack()
7333 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK); in cik_irq_ack()
7335 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
H A Dradeon_dp_mst.c18 EVERGREEN_CRTC4_REGISTER_OFFSET, in radeon_atom_set_enc_offset()
H A Dradeon_device.c706 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | in radeon_card_posted()
H A Devergreen_cs.c1031 EVERGREEN_VLINE_START_END + EVERGREEN_CRTC4_REGISTER_OFFSET, in evergreen_cs_packet_parse_vline()
1039 EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, in evergreen_cs_packet_parse_vline()
H A Datombios_crtc.c2244 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET; in radeon_atombios_init_crtc()
H A Devergreen.c117 EVERGREEN_CRTC4_REGISTER_OFFSET,
H A Dsi.c138 EVERGREEN_CRTC4_REGISTER_OFFSET,