Searched refs:EVERGREEN_CRTC4_REGISTER_OFFSET (Results 1 – 9 of 9) sorted by relevance
/dragonfly/sys/dev/drm/radeon/ |
H A D | evergreen_reg.h | 228 #define EVERGREEN_CRTC4_REGISTER_OFFSET (0x11df0 - 0x6df0) macro
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H A D | radeon_display.c | 1526 EVERGREEN_CRTC4_REGISTER_OFFSET, in radeon_afmt_init() 1878 EVERGREEN_CRTC4_REGISTER_OFFSET); in radeon_get_crtc_scanoutpos() 1880 EVERGREEN_CRTC4_REGISTER_OFFSET); in radeon_get_crtc_scanoutpos()
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H A D | cik.c | 6936 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); in cik_disable_interrupt_state() 6949 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); in cik_disable_interrupt_state() 7219 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5); in cik_irq_set() 7236 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, in cik_irq_set() 7288 EVERGREEN_CRTC4_REGISTER_OFFSET); in cik_irq_ack() 7327 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, in cik_irq_ack() 7333 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK); in cik_irq_ack() 7335 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
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H A D | radeon_dp_mst.c | 18 EVERGREEN_CRTC4_REGISTER_OFFSET, in radeon_atom_set_enc_offset()
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H A D | radeon_device.c | 706 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | in radeon_card_posted()
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H A D | evergreen_cs.c | 1031 EVERGREEN_VLINE_START_END + EVERGREEN_CRTC4_REGISTER_OFFSET, in evergreen_cs_packet_parse_vline() 1039 EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, in evergreen_cs_packet_parse_vline()
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H A D | atombios_crtc.c | 2244 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET; in radeon_atombios_init_crtc()
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H A D | evergreen.c | 117 EVERGREEN_CRTC4_REGISTER_OFFSET,
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H A D | si.c | 138 EVERGREEN_CRTC4_REGISTER_OFFSET,
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