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Searched refs:FBC_DEBUG0__FBC_PERF_MUX1_MASK (Results 1 – 5 of 5) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h6805 #define FBC_DEBUG0__FBC_PERF_MUX1_MASK 0x0000ff00L macro
H A Ddce_8_0_sh_mask.h9807 #define FBC_DEBUG0__FBC_PERF_MUX1_MASK 0xff00 macro
H A Ddce_10_0_sh_mask.h9337 #define FBC_DEBUG0__FBC_PERF_MUX1_MASK 0xff00 macro
H A Ddce_11_0_sh_mask.h9037 #define FBC_DEBUG0__FBC_PERF_MUX1_MASK 0xff00 macro
H A Ddce_11_2_sh_mask.h10293 #define FBC_DEBUG0__FBC_PERF_MUX1_MASK 0xff00 macro