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Searched refs:FEATURE_PCC_LIMIT_CONTROL_BIT (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/drm/amd/powerplay/inc/
H A Dsmu9.h61 #define FEATURE_PCC_LIMIT_CONTROL_BIT 29 macro
97 #define FEATURE_PCC_LIMIT_CONTROL_MASK (1 << FEATURE_PCC_LIMIT_CONTROL_BIT )
/dragonfly/sys/dev/drm/amd/powerplay/hwmgr/
H A Dvega10_hwmgr.c410 data->smu_features[GNLD_PCC_LIMIT].smu_feature_id = FEATURE_PCC_LIMIT_CONTROL_BIT; in vega10_init_dpm_defaults()