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Searched refs:GENERAL_REGS (Results 1 – 25 of 35) sorted by relevance

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/dragonfly/contrib/gcc-4.7/gcc/config/i386/
H A Dconstraints.md31 (define_register_constraint "q" "TARGET_64BIT ? GENERAL_REGS : Q_REGS"
109 "TARGET_PARTIAL_REG_STALL ? NO_REGS : GENERAL_REGS"
115 ? GENERAL_REGS : NO_REGS"
119 "optimize_function_for_speed_p (cfun) ? GENERAL_REGS : NO_REGS"
H A Di386.h1203 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp enumerator
1222 reg_class_subset_p ((CLASS), GENERAL_REGS)
1230 reg_classes_intersect_p ((CLASS), GENERAL_REGS)
1366 #define BASE_REG_CLASS GENERAL_REGS
1374 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \
/dragonfly/contrib/gcc-8.0/gcc/
H A Dreginfo.c862 return GENERAL_REGS; in reg_preferred_class()
905 reg_pref[i].prefclass = GENERAL_REGS; in allocate_reg_info()
907 reg_pref[i].allocnoclass = GENERAL_REGS; in allocate_reg_info()
939 reg_pref[i].prefclass = GENERAL_REGS; in resize_reg_info()
941 reg_pref[i].allocnoclass = GENERAL_REGS; in resize_reg_info()
H A Dira.c853 || cl2 == (int) GENERAL_REGS)) in setup_pressure_classes()
862 || cl == (int) GENERAL_REGS)) in setup_pressure_classes()
1018 else if (i == GENERAL_REGS) in setup_allocno_and_important_classes()
1295 && (cl3 == GENERAL_REGS in setup_reg_class_relations()
1297 != GENERAL_REGS) in setup_reg_class_relations()
1334 || cl3 == GENERAL_REGS in setup_reg_class_relations()
1338 || (ira_reg_class_subunion[cl1][cl2] != GENERAL_REGS in setup_reg_class_relations()
1359 || cl3 == GENERAL_REGS in setup_reg_class_relations()
1363 || (ira_reg_class_superunion[cl1][cl2] != GENERAL_REGS in setup_reg_class_relations()
2798 setup_reg_classes (i, GENERAL_REGS, ALL_REGS, GENERAL_REGS); in expand_reg_info()
H A Dcommon.md20 (define_register_constraint "r" "GENERAL_REGS"
H A Dregstat.c448 if (rclass != GENERAL_REGS || altclass != ALL_REGS) in dump_reg_info()
H A Dcfgloopanal.c352 if (TEST_HARD_REG_BIT (reg_class_contents[GENERAL_REGS], i) in init_set_costs()
H A Dloop-invariant.c1284 pressure_class = GENERAL_REGS; in get_pressure_class_and_nregs()
1888 GENERAL_REGS, NO_REGS, GENERAL_REGS); in move_invariants()
H A Drecog.c2411 reg_class_subunion[(int) op_alt[i].cl][(int) GENERAL_REGS]; in preprocess_constraints()
2715 || GENERAL_REGS == ALL_REGS in constrain_operands()
2718 || reg_fits_class_p (op, GENERAL_REGS, offset, mode)) in constrain_operands()
H A Dira-costs.c760 classes[i] = ira_reg_class_subunion[classes[i]][GENERAL_REGS]; in record_reg_classes()
1479 enum reg_class cl = GENERAL_REGS; in scan_one_insn()
H A Dpostreload.c534 rclass = reg_class_subunion[rclass][GENERAL_REGS]; in reload_cse_simplify_operands()
/dragonfly/contrib/gcc-4.7/gcc/
H A Dira.c851 || cl2 == (int) GENERAL_REGS)) in setup_pressure_classes()
859 || cl == (int) GENERAL_REGS)) in setup_pressure_classes()
975 else if (i == GENERAL_REGS) in setup_allocno_and_important_classes()
1255 && (cl3 == GENERAL_REGS in setup_reg_class_relations()
1256 || (ira_reg_class_intersect[cl1][cl2] != GENERAL_REGS in setup_reg_class_relations()
1277 || cl3 == GENERAL_REGS in setup_reg_class_relations()
1281 || (ira_reg_class_subunion[cl1][cl2] != GENERAL_REGS in setup_reg_class_relations()
1302 || cl3 == GENERAL_REGS in setup_reg_class_relations()
1306 || (ira_reg_class_superunion[cl1][cl2] != GENERAL_REGS in setup_reg_class_relations()
2252 setup_reg_classes (i, GENERAL_REGS, ALL_REGS, GENERAL_REGS); in expand_reg_info()
H A Dtarghooks.c887 = (insn_letter == 'r' ? GENERAL_REGS in default_secondary_reload()
905 = (scratch_letter == 'r' ? GENERAL_REGS in default_secondary_reload()
H A Dcfgloopanal.c341 if (TEST_HARD_REG_BIT (reg_class_contents[GENERAL_REGS], i) in init_set_costs()
H A Dloop-invariant.c1039 pressure_class = GENERAL_REGS; in get_pressure_class_and_nregs()
1529 GENERAL_REGS, NO_REGS, GENERAL_REGS); in move_invariants()
H A Drecog.c2277 reg_class_subunion[(int) op_alt[j].cl][(int) GENERAL_REGS]; in preprocess_constraints()
2516 || GENERAL_REGS == ALL_REGS in constrain_operands()
2519 || reg_fits_class_p (op, GENERAL_REGS, offset, mode)) in constrain_operands()
2646 ? GENERAL_REGS : REG_CLASS_FROM_CONSTRAINT (c, p)); in constrain_operands()
3077 cl = (class_str[0] == 'r' ? GENERAL_REGS in peep2_find_free_register()
H A Dira-lives.c833 ? GENERAL_REGS in single_reg_class()
923 ? GENERAL_REGS in ira_implicitly_set_insn_hard_regs()
H A Dira-conflicts.c320 ? GENERAL_REGS : REG_CLASS_FROM_CONSTRAINT (c, str)); in get_dup_num()
H A Dira-costs.c726 classes[i] = ira_reg_class_subunion[classes[i]][GENERAL_REGS]; in record_reg_classes()
1325 enum reg_class cl = GENERAL_REGS; in scan_one_insn()
H A Dreginfo.c962 return GENERAL_REGS; in reg_preferred_class()
H A Dcfg.c653 if (rclass != GENERAL_REGS || altclass != ALL_REGS) in dump_reg_info()
H A Dreload.c406 scratch_class = (letter == 'r' ? GENERAL_REGS in push_secondary_reload()
565 return GENERAL_REGS; in scratch_reload_class()
3394 && (GENERAL_REGS == ALL_REGS in find_reloads()
3403 = reg_class_subunion[this_alternative[i]][(int) GENERAL_REGS]; in find_reloads()
H A Dpostreload.c563 rclass = reg_class_subunion[(int) rclass][(int) GENERAL_REGS]; in reload_cse_simplify_operands()
/dragonfly/contrib/gcc-8.0/gcc/config/i386/
H A Dconstraints.md31 (define_register_constraint "q" "TARGET_64BIT ? GENERAL_REGS : Q_REGS"
159 "TARGET_PARTIAL_REG_STALL ? NO_REGS : GENERAL_REGS"
164 ? NO_REGS : GENERAL_REGS"
H A Di386.h1332 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp enumerator
1358 reg_class_subset_p ((CLASS), GENERAL_REGS)
1368 reg_classes_intersect_p ((CLASS), GENERAL_REGS)
1546 #define BASE_REG_CLASS GENERAL_REGS

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