/dragonfly/contrib/gcc-4.7/gcc/config/i386/ |
H A D | constraints.md | 31 (define_register_constraint "q" "TARGET_64BIT ? GENERAL_REGS : Q_REGS" 109 "TARGET_PARTIAL_REG_STALL ? NO_REGS : GENERAL_REGS" 115 ? GENERAL_REGS : NO_REGS" 119 "optimize_function_for_speed_p (cfun) ? GENERAL_REGS : NO_REGS"
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H A D | i386.h | 1203 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp enumerator 1222 reg_class_subset_p ((CLASS), GENERAL_REGS) 1230 reg_classes_intersect_p ((CLASS), GENERAL_REGS) 1366 #define BASE_REG_CLASS GENERAL_REGS 1374 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \
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/dragonfly/contrib/gcc-8.0/gcc/ |
H A D | reginfo.c | 862 return GENERAL_REGS; in reg_preferred_class() 905 reg_pref[i].prefclass = GENERAL_REGS; in allocate_reg_info() 907 reg_pref[i].allocnoclass = GENERAL_REGS; in allocate_reg_info() 939 reg_pref[i].prefclass = GENERAL_REGS; in resize_reg_info() 941 reg_pref[i].allocnoclass = GENERAL_REGS; in resize_reg_info()
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H A D | ira.c | 853 || cl2 == (int) GENERAL_REGS)) in setup_pressure_classes() 862 || cl == (int) GENERAL_REGS)) in setup_pressure_classes() 1018 else if (i == GENERAL_REGS) in setup_allocno_and_important_classes() 1295 && (cl3 == GENERAL_REGS in setup_reg_class_relations() 1297 != GENERAL_REGS) in setup_reg_class_relations() 1334 || cl3 == GENERAL_REGS in setup_reg_class_relations() 1338 || (ira_reg_class_subunion[cl1][cl2] != GENERAL_REGS in setup_reg_class_relations() 1359 || cl3 == GENERAL_REGS in setup_reg_class_relations() 1363 || (ira_reg_class_superunion[cl1][cl2] != GENERAL_REGS in setup_reg_class_relations() 2798 setup_reg_classes (i, GENERAL_REGS, ALL_REGS, GENERAL_REGS); in expand_reg_info()
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H A D | common.md | 20 (define_register_constraint "r" "GENERAL_REGS"
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H A D | regstat.c | 448 if (rclass != GENERAL_REGS || altclass != ALL_REGS) in dump_reg_info()
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H A D | cfgloopanal.c | 352 if (TEST_HARD_REG_BIT (reg_class_contents[GENERAL_REGS], i) in init_set_costs()
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H A D | loop-invariant.c | 1284 pressure_class = GENERAL_REGS; in get_pressure_class_and_nregs() 1888 GENERAL_REGS, NO_REGS, GENERAL_REGS); in move_invariants()
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H A D | recog.c | 2411 reg_class_subunion[(int) op_alt[i].cl][(int) GENERAL_REGS]; in preprocess_constraints() 2715 || GENERAL_REGS == ALL_REGS in constrain_operands() 2718 || reg_fits_class_p (op, GENERAL_REGS, offset, mode)) in constrain_operands()
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H A D | ira-costs.c | 760 classes[i] = ira_reg_class_subunion[classes[i]][GENERAL_REGS]; in record_reg_classes() 1479 enum reg_class cl = GENERAL_REGS; in scan_one_insn()
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H A D | postreload.c | 534 rclass = reg_class_subunion[rclass][GENERAL_REGS]; in reload_cse_simplify_operands()
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/dragonfly/contrib/gcc-4.7/gcc/ |
H A D | ira.c | 851 || cl2 == (int) GENERAL_REGS)) in setup_pressure_classes() 859 || cl == (int) GENERAL_REGS)) in setup_pressure_classes() 975 else if (i == GENERAL_REGS) in setup_allocno_and_important_classes() 1255 && (cl3 == GENERAL_REGS in setup_reg_class_relations() 1256 || (ira_reg_class_intersect[cl1][cl2] != GENERAL_REGS in setup_reg_class_relations() 1277 || cl3 == GENERAL_REGS in setup_reg_class_relations() 1281 || (ira_reg_class_subunion[cl1][cl2] != GENERAL_REGS in setup_reg_class_relations() 1302 || cl3 == GENERAL_REGS in setup_reg_class_relations() 1306 || (ira_reg_class_superunion[cl1][cl2] != GENERAL_REGS in setup_reg_class_relations() 2252 setup_reg_classes (i, GENERAL_REGS, ALL_REGS, GENERAL_REGS); in expand_reg_info()
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H A D | targhooks.c | 887 = (insn_letter == 'r' ? GENERAL_REGS in default_secondary_reload() 905 = (scratch_letter == 'r' ? GENERAL_REGS in default_secondary_reload()
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H A D | cfgloopanal.c | 341 if (TEST_HARD_REG_BIT (reg_class_contents[GENERAL_REGS], i) in init_set_costs()
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H A D | loop-invariant.c | 1039 pressure_class = GENERAL_REGS; in get_pressure_class_and_nregs() 1529 GENERAL_REGS, NO_REGS, GENERAL_REGS); in move_invariants()
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H A D | recog.c | 2277 reg_class_subunion[(int) op_alt[j].cl][(int) GENERAL_REGS]; in preprocess_constraints() 2516 || GENERAL_REGS == ALL_REGS in constrain_operands() 2519 || reg_fits_class_p (op, GENERAL_REGS, offset, mode)) in constrain_operands() 2646 ? GENERAL_REGS : REG_CLASS_FROM_CONSTRAINT (c, p)); in constrain_operands() 3077 cl = (class_str[0] == 'r' ? GENERAL_REGS in peep2_find_free_register()
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H A D | ira-lives.c | 833 ? GENERAL_REGS in single_reg_class() 923 ? GENERAL_REGS in ira_implicitly_set_insn_hard_regs()
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H A D | ira-conflicts.c | 320 ? GENERAL_REGS : REG_CLASS_FROM_CONSTRAINT (c, str)); in get_dup_num()
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H A D | ira-costs.c | 726 classes[i] = ira_reg_class_subunion[classes[i]][GENERAL_REGS]; in record_reg_classes() 1325 enum reg_class cl = GENERAL_REGS; in scan_one_insn()
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H A D | reginfo.c | 962 return GENERAL_REGS; in reg_preferred_class()
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H A D | cfg.c | 653 if (rclass != GENERAL_REGS || altclass != ALL_REGS) in dump_reg_info()
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H A D | reload.c | 406 scratch_class = (letter == 'r' ? GENERAL_REGS in push_secondary_reload() 565 return GENERAL_REGS; in scratch_reload_class() 3394 && (GENERAL_REGS == ALL_REGS in find_reloads() 3403 = reg_class_subunion[this_alternative[i]][(int) GENERAL_REGS]; in find_reloads()
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H A D | postreload.c | 563 rclass = reg_class_subunion[(int) rclass][(int) GENERAL_REGS]; in reload_cse_simplify_operands()
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/dragonfly/contrib/gcc-8.0/gcc/config/i386/ |
H A D | constraints.md | 31 (define_register_constraint "q" "TARGET_64BIT ? GENERAL_REGS : Q_REGS" 159 "TARGET_PARTIAL_REG_STALL ? NO_REGS : GENERAL_REGS" 164 ? NO_REGS : GENERAL_REGS"
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H A D | i386.h | 1332 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp enumerator 1358 reg_class_subset_p ((CLASS), GENERAL_REGS) 1368 reg_classes_intersect_p ((CLASS), GENERAL_REGS) 1546 #define BASE_REG_CLASS GENERAL_REGS
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