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Searched refs:GENFC_WT__VSYNC_SEL_W__SHIFT (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h7148 #define GENFC_WT__VSYNC_SEL_W__SHIFT 0x00000003 macro
H A Ddce_8_0_sh_mask.h10632 #define GENFC_WT__VSYNC_SEL_W__SHIFT 0x3 macro
H A Ddce_10_0_sh_mask.h11016 #define GENFC_WT__VSYNC_SEL_W__SHIFT 0x3 macro
H A Ddce_11_0_sh_mask.h10828 #define GENFC_WT__VSYNC_SEL_W__SHIFT 0x3 macro
H A Ddce_11_2_sh_mask.h12082 #define GENFC_WT__VSYNC_SEL_W__SHIFT 0x3 macro
H A Ddce_12_0_sh_mask.h2182 #define GENFC_WT__VSYNC_SEL_W__SHIFT … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_sh_mask.h821 #define GENFC_WT__VSYNC_SEL_W__SHIFT … macro