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Searched refs:GENMO_RD__VGA_VSYNC_POL_MASK (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h7159 #define GENMO_RD__VGA_VSYNC_POL_MASK 0x00000080L macro
H A Ddce_8_0_sh_mask.h10627 #define GENMO_RD__VGA_VSYNC_POL_MASK 0x80 macro
H A Ddce_10_0_sh_mask.h11011 #define GENMO_RD__VGA_VSYNC_POL_MASK 0x80 macro
H A Ddce_11_0_sh_mask.h10823 #define GENMO_RD__VGA_VSYNC_POL_MASK 0x80 macro
H A Ddce_11_2_sh_mask.h12077 #define GENMO_RD__VGA_VSYNC_POL_MASK 0x80 macro
H A Ddce_12_0_sh_mask.h2256 #define GENMO_RD__VGA_VSYNC_POL_MASK … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_sh_mask.h895 #define GENMO_RD__VGA_VSYNC_POL_MASK … macro