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Searched refs:GRBM_GFX_INDEX (Results 1 – 18 of 18) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dvce_v4_0.c709 WREG32_FIELD(GRBM_GFX_INDEX, INSTANCE_INDEX, 0);
714 WREG32_FIELD(GRBM_GFX_INDEX, INSTANCE_INDEX, 0x10);
719 WREG32_FIELD(GRBM_GFX_INDEX, INSTANCE_INDEX, 0);
901 WREG32_FIELD(GRBM_GFX_INDEX, VCE_INSTANCE, i);
920 WREG32_FIELD(GRBM_GFX_INDEX, VCE_INSTANCE, 0);
H A Damdgpu_amdkfd_gfx_v8.c748 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute()
750 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute()
752 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute()
H A Damdgpu_amdkfd_gfx_v9.c934 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute()
936 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute()
938 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute()
H A Dgfx_v9_0.c1676 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); in gfx_v9_0_select_se_sh()
1678 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); in gfx_v9_0_select_se_sh()
1681 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); in gfx_v9_0_select_se_sh()
1683 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v9_0_select_se_sh()
1686 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1); in gfx_v9_0_select_se_sh()
1688 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v9_0_select_se_sh()
H A Dvce_v3_0.c829 WREG32_FIELD(GRBM_GFX_INDEX, VCE_INSTANCE, 0); in vce_v3_0_get_clockgating_state()
H A Dgfx_v8_0.c3554 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); in gfx_v8_0_select_se_sh()
3556 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); in gfx_v8_0_select_se_sh()
3559 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); in gfx_v8_0_select_se_sh()
3561 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v8_0_select_se_sh()
3564 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1); in gfx_v8_0_select_se_sh()
3566 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v8_0_select_se_sh()
/dragonfly/sys/dev/drm/radeon/
H A Dcypress_dpm.c126 WREG32(GRBM_GFX_INDEX, 0xC0000000); in cypress_gfx_clock_gating_enable()
153 WREG32(GRBM_GFX_INDEX, 0xC0000000); in cypress_gfx_clock_gating_enable()
187 WREG32(GRBM_GFX_INDEX, 0xC0000000); in cypress_mg_clock_gating_enable()
208 WREG32(GRBM_GFX_INDEX, 0xC0000000); in cypress_mg_clock_gating_enable()
H A Dni.c1105 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); in cayman_gpu_init()
1125 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); in cayman_gpu_init()
1134 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); in cayman_gpu_init()
H A Dnid.h295 #define GRBM_GFX_INDEX 0x802C macro
H A Dsid.h998 #define GRBM_GFX_INDEX 0x802C macro
H A Dcikd.h1627 #define GRBM_GFX_INDEX 0x30800 macro
H A Devergreen.c3447 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); in evergreen_gpu_init()
3468 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); in evergreen_gpu_init()
3477 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); in evergreen_gpu_init()
H A Devergreend.h412 #define GRBM_GFX_INDEX 0x802C macro
H A Dsi.c2950 WREG32(GRBM_GFX_INDEX, data); in si_select_se_sh()
4409 case GRBM_GFX_INDEX: in si_vm_reg_valid()
H A Devergreen_cs.c3233 case GRBM_GFX_INDEX: in evergreen_vm_reg_valid()
H A Dcik.c3067 WREG32(GRBM_GFX_INDEX, data); in cik_select_se_sh()
/dragonfly/sys/dev/drm/radeon/reg_srcs/
H A Devergreen2 0x0000802C GRBM_GFX_INDEX
H A Dcayman2 0x0000802C GRBM_GFX_INDEX