/dragonfly/sys/dev/drm/amd/amdgpu/ |
H A D | vce_v4_0.c | 709 WREG32_FIELD(GRBM_GFX_INDEX, INSTANCE_INDEX, 0); 714 WREG32_FIELD(GRBM_GFX_INDEX, INSTANCE_INDEX, 0x10); 719 WREG32_FIELD(GRBM_GFX_INDEX, INSTANCE_INDEX, 0); 901 WREG32_FIELD(GRBM_GFX_INDEX, VCE_INSTANCE, i); 920 WREG32_FIELD(GRBM_GFX_INDEX, VCE_INSTANCE, 0);
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H A D | amdgpu_amdkfd_gfx_v8.c | 748 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute() 750 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute() 752 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute()
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H A D | amdgpu_amdkfd_gfx_v9.c | 934 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute() 936 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute() 938 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute()
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H A D | gfx_v9_0.c | 1676 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); in gfx_v9_0_select_se_sh() 1678 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); in gfx_v9_0_select_se_sh() 1681 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); in gfx_v9_0_select_se_sh() 1683 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v9_0_select_se_sh() 1686 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1); in gfx_v9_0_select_se_sh() 1688 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v9_0_select_se_sh()
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H A D | vce_v3_0.c | 829 WREG32_FIELD(GRBM_GFX_INDEX, VCE_INSTANCE, 0); in vce_v3_0_get_clockgating_state()
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H A D | gfx_v8_0.c | 3554 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); in gfx_v8_0_select_se_sh() 3556 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); in gfx_v8_0_select_se_sh() 3559 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); in gfx_v8_0_select_se_sh() 3561 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v8_0_select_se_sh() 3564 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1); in gfx_v8_0_select_se_sh() 3566 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v8_0_select_se_sh()
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/dragonfly/sys/dev/drm/radeon/ |
H A D | cypress_dpm.c | 126 WREG32(GRBM_GFX_INDEX, 0xC0000000); in cypress_gfx_clock_gating_enable() 153 WREG32(GRBM_GFX_INDEX, 0xC0000000); in cypress_gfx_clock_gating_enable() 187 WREG32(GRBM_GFX_INDEX, 0xC0000000); in cypress_mg_clock_gating_enable() 208 WREG32(GRBM_GFX_INDEX, 0xC0000000); in cypress_mg_clock_gating_enable()
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H A D | ni.c | 1105 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); in cayman_gpu_init() 1125 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); in cayman_gpu_init() 1134 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); in cayman_gpu_init()
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H A D | nid.h | 295 #define GRBM_GFX_INDEX 0x802C macro
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H A D | sid.h | 998 #define GRBM_GFX_INDEX 0x802C macro
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H A D | cikd.h | 1627 #define GRBM_GFX_INDEX 0x30800 macro
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H A D | evergreen.c | 3447 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); in evergreen_gpu_init() 3468 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); in evergreen_gpu_init() 3477 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); in evergreen_gpu_init()
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H A D | evergreend.h | 412 #define GRBM_GFX_INDEX 0x802C macro
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H A D | si.c | 2950 WREG32(GRBM_GFX_INDEX, data); in si_select_se_sh() 4409 case GRBM_GFX_INDEX: in si_vm_reg_valid()
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H A D | evergreen_cs.c | 3233 case GRBM_GFX_INDEX: in evergreen_vm_reg_valid()
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H A D | cik.c | 3067 WREG32(GRBM_GFX_INDEX, data); in cik_select_se_sh()
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/dragonfly/sys/dev/drm/radeon/reg_srcs/ |
H A D | evergreen | 2 0x0000802C GRBM_GFX_INDEX
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H A D | cayman | 2 0x0000802C GRBM_GFX_INDEX
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