Searched refs:HDMI_ACR_32_0 (Results 1 – 9 of 9) sorted by relevance
| /dragonfly/sys/dev/drm/amd/display/dc/dce/ |
| H A D | dce_stream_encoder.h | 77 SRI(HDMI_ACR_32_0, DIG, id),\
181 SE_SF(HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\
676 uint32_t HDMI_ACR_32_0; member
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| H A D | dce_stream_encoder.c | 1363 REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz); in dce110_se_setup_hdmi_audio()
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| /dragonfly/sys/dev/drm/amd/display/dc/dcn10/ |
| H A D | dcn10_stream_encoder.h | 67 SRI(HDMI_ACR_32_0, DIG, id),\
145 uint32_t HDMI_ACR_32_0; member
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| H A D | dcn10_stream_encoder.c | 1218 REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz); in enc1_se_setup_hdmi_audio()
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| /dragonfly/sys/dev/drm/radeon/ |
| H A D | evergreen_hdmi.c | 92 WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr->cts_32khz)); in evergreen_hdmi_update_acr()
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| H A D | rv770d.h | 787 #define HDMI_ACR_32_0 0x74ac macro
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| H A D | evergreend.h | 641 #define HDMI_ACR_32_0 0x70dc macro
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| /dragonfly/sys/dev/drm/amd/amdgpu/ |
| H A D | dce_v10_0.c | 1467 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz); in dce_v10_0_afmt_update_ACR()
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| H A D | dce_v11_0.c | 1509 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz); in dce_v11_0_afmt_update_ACR()
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