Home
last modified time | relevance | path

Searched refs:HDMI_ACR_CTS_48 (Results 1 – 9 of 9) sorted by relevance

/dragonfly/sys/dev/drm/amd/display/dc/dce/
H A Ddce_stream_encoder.h185 SE_SF(HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\
264 SE_SF(DIG0_HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\
459 uint8_t HDMI_ACR_CTS_48; member
589 uint32_t HDMI_ACR_CTS_48; member
H A Ddce_stream_encoder.c1375 REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz); in dce110_se_setup_hdmi_audio()
/dragonfly/sys/dev/drm/amd/display/dc/dcn10/
H A Ddcn10_stream_encoder.h216 SE_SF(DIG0_HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\
390 type HDMI_ACR_CTS_48;\
H A Ddcn10_stream_encoder.c1230 REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz); in enc1_se_setup_hdmi_audio()
/dragonfly/sys/dev/drm/radeon/
H A Devergreen_hdmi.c98 WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr->cts_48khz)); in evergreen_hdmi_update_acr()
H A Drv770d.h796 # define HDMI_ACR_CTS_48(x) (((x) & 0xfffff) << 12) macro
H A Devergreend.h650 # define HDMI_ACR_CTS_48(x) (((x) & 0xfffff) << 12) macro
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Ddce_v10_0.c1481 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz); in dce_v10_0_afmt_update_ACR()
H A Ddce_v11_0.c1523 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz); in dce_v11_0_afmt_update_ACR()