Searched refs:HDMI_ACR_CTS_48 (Results 1 – 9 of 9) sorted by relevance
/dragonfly/sys/dev/drm/amd/display/dc/dce/ |
H A D | dce_stream_encoder.h | 185 SE_SF(HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\ 264 SE_SF(DIG0_HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\ 459 uint8_t HDMI_ACR_CTS_48; member 589 uint32_t HDMI_ACR_CTS_48; member
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H A D | dce_stream_encoder.c | 1375 REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz); in dce110_se_setup_hdmi_audio()
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/dragonfly/sys/dev/drm/amd/display/dc/dcn10/ |
H A D | dcn10_stream_encoder.h | 216 SE_SF(DIG0_HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\ 390 type HDMI_ACR_CTS_48;\
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H A D | dcn10_stream_encoder.c | 1230 REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz); in enc1_se_setup_hdmi_audio()
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/dragonfly/sys/dev/drm/radeon/ |
H A D | evergreen_hdmi.c | 98 WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr->cts_48khz)); in evergreen_hdmi_update_acr()
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H A D | rv770d.h | 796 # define HDMI_ACR_CTS_48(x) (((x) & 0xfffff) << 12) macro
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H A D | evergreend.h | 650 # define HDMI_ACR_CTS_48(x) (((x) & 0xfffff) << 12) macro
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/dragonfly/sys/dev/drm/amd/amdgpu/ |
H A D | dce_v10_0.c | 1481 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz); in dce_v10_0_afmt_update_ACR()
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H A D | dce_v11_0.c | 1523 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz); in dce_v11_0_afmt_update_ACR()
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