Home
last modified time | relevance | path

Searched refs:HDMI_ACR_N_32 (Results 1 – 8 of 8) sorted by relevance

/dragonfly/sys/dev/drm/amd/display/dc/dce/
H A Ddce_stream_encoder.h182 SE_SF(HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\
261 SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\
456 uint8_t HDMI_ACR_N_32; member
586 uint32_t HDMI_ACR_N_32; member
H A Ddce_stream_encoder.c1366 REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz); in dce110_se_setup_hdmi_audio()
/dragonfly/sys/dev/drm/amd/display/dc/dcn10/
H A Ddcn10_stream_encoder.h213 SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\
387 type HDMI_ACR_N_32;\
H A Ddcn10_stream_encoder.c1221 REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz); in enc1_se_setup_hdmi_audio()
/dragonfly/sys/dev/drm/radeon/
H A Drv770d.h790 # define HDMI_ACR_N_32(x) (((x) & 0xfffff) << 0) macro
H A Devergreend.h644 # define HDMI_ACR_N_32(x) (((x) & 0xfffff) << 0) macro
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Ddce_v10_0.c1470 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); in dce_v10_0_afmt_update_ACR()
H A Ddce_v11_0.c1512 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); in dce_v11_0_afmt_update_ACR()