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Searched refs:HDMI_ACR_N_44 (Results 1 – 8 of 8) sorted by relevance

/dragonfly/sys/dev/drm/amd/display/dc/dce/
H A Ddce_stream_encoder.h184 SE_SF(HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
263 SE_SF(DIG0_HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
458 uint8_t HDMI_ACR_N_44; member
588 uint32_t HDMI_ACR_N_44; member
H A Ddce_stream_encoder.c1372 REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz); in dce110_se_setup_hdmi_audio()
/dragonfly/sys/dev/drm/amd/display/dc/dcn10/
H A Ddcn10_stream_encoder.h215 SE_SF(DIG0_HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
389 type HDMI_ACR_N_44;\
H A Ddcn10_stream_encoder.c1227 REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz); in enc1_se_setup_hdmi_audio()
/dragonfly/sys/dev/drm/radeon/
H A Drv770d.h794 # define HDMI_ACR_N_44(x) (((x) & 0xfffff) << 0) macro
H A Devergreend.h648 # define HDMI_ACR_N_44(x) (((x) & 0xfffff) << 0) macro
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Ddce_v10_0.c1477 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); in dce_v10_0_afmt_update_ACR()
H A Ddce_v11_0.c1519 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); in dce_v11_0_afmt_update_ACR()