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Searched refs:HDMI_ACR_N_48 (Results 1 – 8 of 8) sorted by relevance

/dragonfly/sys/dev/drm/amd/display/dc/dce/
H A Ddce_stream_encoder.h186 SE_SF(HDMI_ACR_48_1, HDMI_ACR_N_48, mask_sh),\
265 SE_SF(DIG0_HDMI_ACR_48_1, HDMI_ACR_N_48, mask_sh),\
460 uint8_t HDMI_ACR_N_48; member
590 uint32_t HDMI_ACR_N_48; member
H A Ddce_stream_encoder.c1378 REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz); in dce110_se_setup_hdmi_audio()
/dragonfly/sys/dev/drm/amd/display/dc/dcn10/
H A Ddcn10_stream_encoder.h217 SE_SF(DIG0_HDMI_ACR_48_1, HDMI_ACR_N_48, mask_sh),\
391 type HDMI_ACR_N_48;\
H A Ddcn10_stream_encoder.c1233 REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz); in enc1_se_setup_hdmi_audio()
/dragonfly/sys/dev/drm/radeon/
H A Drv770d.h798 # define HDMI_ACR_N_48(x) (((x) & 0xfffff) << 0) macro
H A Devergreend.h652 # define HDMI_ACR_N_48(x) (((x) & 0xfffff) << 0) macro
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Ddce_v10_0.c1484 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz); in dce_v10_0_afmt_update_ACR()
H A Ddce_v11_0.c1526 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz); in dce_v11_0_afmt_update_ACR()