Searched refs:HDMI_ACR_PACKET_CONTROL (Results 1 – 9 of 9) sorted by relevance
/dragonfly/sys/dev/drm/amd/display/dc/dce/ |
H A D | dce_stream_encoder.h | 76 SRI(HDMI_ACR_PACKET_CONTROL, DIG, id),\ 178 SE_SF(HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, mask_sh),\ 179 SE_SF(HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\ 180 SE_SF(HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUDIO_PRIORITY, mask_sh),\ 675 uint32_t HDMI_ACR_PACKET_CONTROL; member
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H A D | dce_stream_encoder.c | 1346 REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL, in dce110_se_setup_hdmi_audio()
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/dragonfly/sys/dev/drm/radeon/ |
H A D | evergreen_hdmi.c | 85 WREG32(HDMI_ACR_PACKET_CONTROL + offset, in evergreen_hdmi_update_acr() 88 WREG32(HDMI_ACR_PACKET_CONTROL + offset, in evergreen_hdmi_update_acr()
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H A D | rv770d.h | 693 #define HDMI_ACR_PACKET_CONTROL 0x740c macro
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H A D | evergreend.h | 538 #define HDMI_ACR_PACKET_CONTROL 0x703c macro
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/dragonfly/sys/dev/drm/amd/display/dc/dcn10/ |
H A D | dcn10_stream_encoder.h | 66 SRI(HDMI_ACR_PACKET_CONTROL, DIG, id),\ 144 uint32_t HDMI_ACR_PACKET_CONTROL; member
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H A D | dcn10_stream_encoder.c | 1201 REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL, in enc1_se_setup_hdmi_audio()
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/dragonfly/sys/dev/drm/amd/amdgpu/ |
H A D | dce_v10_0.c | 1648 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0); in dce_v10_0_afmt_setmode() 1651 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1); in dce_v10_0_afmt_setmode() 1653 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1); in dce_v10_0_afmt_setmode()
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H A D | dce_v11_0.c | 1690 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0); in dce_v11_0_afmt_setmode() 1693 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1); in dce_v11_0_afmt_setmode() 1695 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1); in dce_v11_0_afmt_setmode()
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