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Searched refs:HDMI_CONTROL (Results 1 – 9 of 9) sorted by relevance

/dragonfly/sys/dev/drm/amd/display/dc/dcn10/
H A Ddcn10_stream_encoder.c501 REG_UPDATE_5(HDMI_CONTROL, in enc1_stream_encoder_hdmi_set_stream_attribute()
511 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); in enc1_stream_encoder_hdmi_set_stream_attribute()
515 REG_UPDATE_2(HDMI_CONTROL, in enc1_stream_encoder_hdmi_set_stream_attribute()
519 REG_UPDATE_2(HDMI_CONTROL, in enc1_stream_encoder_hdmi_set_stream_attribute()
526 REG_UPDATE_2(HDMI_CONTROL, in enc1_stream_encoder_hdmi_set_stream_attribute()
530 REG_UPDATE_2(HDMI_CONTROL, in enc1_stream_encoder_hdmi_set_stream_attribute()
536 REG_UPDATE_2(HDMI_CONTROL, in enc1_stream_encoder_hdmi_set_stream_attribute()
549 REG_UPDATE_2(HDMI_CONTROL, in enc1_stream_encoder_hdmi_set_stream_attribute()
561 REG_UPDATE_2(HDMI_CONTROL, in enc1_stream_encoder_hdmi_set_stream_attribute()
H A Ddcn10_stream_encoder.h55 SRI(HDMI_CONTROL, DIG, id), \
132 uint32_t HDMI_CONTROL; member
/dragonfly/sys/dev/drm/amd/display/dc/dce/
H A Ddce_stream_encoder.c562 REG_UPDATE_3(HDMI_CONTROL, in dce110_stream_encoder_hdmi_set_stream_attribute()
567 REG_UPDATE_5(HDMI_CONTROL, in dce110_stream_encoder_hdmi_set_stream_attribute()
577 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); in dce110_stream_encoder_hdmi_set_stream_attribute()
581 REG_UPDATE_2(HDMI_CONTROL, in dce110_stream_encoder_hdmi_set_stream_attribute()
585 REG_UPDATE_2(HDMI_CONTROL, in dce110_stream_encoder_hdmi_set_stream_attribute()
592 REG_UPDATE_2(HDMI_CONTROL, in dce110_stream_encoder_hdmi_set_stream_attribute()
596 REG_UPDATE_2(HDMI_CONTROL, in dce110_stream_encoder_hdmi_set_stream_attribute()
602 REG_UPDATE_2(HDMI_CONTROL, in dce110_stream_encoder_hdmi_set_stream_attribute()
616 REG_UPDATE_2(HDMI_CONTROL, in dce110_stream_encoder_hdmi_set_stream_attribute()
628 REG_UPDATE_2(HDMI_CONTROL, in dce110_stream_encoder_hdmi_set_stream_attribute()
H A Ddce_stream_encoder.h68 SRI(HDMI_CONTROL, DIG, id), \
136 SE_SF(HDMI_CONTROL, HDMI_PACKET_GEN_VERSION, mask_sh),\
137 SE_SF(HDMI_CONTROL, HDMI_KEEPOUT_MODE, mask_sh),\
138 SE_SF(HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, mask_sh),\
139 SE_SF(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, mask_sh),\
300 SE_SF(HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\
301 SE_SF(HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\
310 SE_SF(HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\
311 SE_SF(HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\
665 uint32_t HDMI_CONTROL; member
/dragonfly/sys/dev/drm/radeon/
H A Devergreen_hdmi.c345 val = RREG32(HDMI_CONTROL + offset); in dce4_hdmi_set_color_depth()
372 WREG32(HDMI_CONTROL + offset, val); in dce4_hdmi_set_color_depth()
H A Drv770d.h681 #define HDMI_CONTROL 0x7400 macro
H A Devergreend.h520 #define HDMI_CONTROL 0x7030 macro
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Ddce_v10_0.c1588 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0); in dce_v10_0_afmt_setmode()
1589 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); in dce_v10_0_afmt_setmode()
1594 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); in dce_v10_0_afmt_setmode()
1595 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1); in dce_v10_0_afmt_setmode()
1600 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); in dce_v10_0_afmt_setmode()
1601 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2); in dce_v10_0_afmt_setmode()
H A Ddce_v11_0.c1630 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0); in dce_v11_0_afmt_setmode()
1631 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); in dce_v11_0_afmt_setmode()
1636 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); in dce_v11_0_afmt_setmode()
1637 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1); in dce_v11_0_afmt_setmode()
1642 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); in dce_v11_0_afmt_setmode()
1643 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2); in dce_v11_0_afmt_setmode()