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Searched refs:HDMI_INFOFRAME_CONTROL1 (Results 1 – 9 of 9) sorted by relevance

/dragonfly/sys/dev/drm/amd/display/dc/dce/
H A Ddce_stream_encoder.h73 SRI(HDMI_INFOFRAME_CONTROL1, DIG, id), \
145 SE_SF(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, mask_sh),\
153 SE_SF(HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, mask_sh),\
672 uint32_t HDMI_INFOFRAME_CONTROL1; member
H A Ddce_stream_encoder.c644 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, in dce110_stream_encoder_hdmi_set_stream_attribute()
736 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, in dce110_stream_encoder_update_hdmi_info_packets()
/dragonfly/sys/dev/drm/amd/display/dc/dcn10/
H A Ddcn10_stream_encoder.h63 SRI(HDMI_INFOFRAME_CONTROL1, DIG, id), \
141 uint32_t HDMI_INFOFRAME_CONTROL1; member
H A Ddcn10_stream_encoder.c577 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, in enc1_stream_encoder_hdmi_set_stream_attribute()
/dragonfly/sys/dev/drm/radeon/
H A Devergreen_hdmi.c237 WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset, in evergreen_set_avi_packet()
H A Drv770d.h714 #define HDMI_INFOFRAME_CONTROL1 0x7418 macro
H A Devergreend.h564 #define HDMI_INFOFRAME_CONTROL1 0x7048 macro
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Ddce_v10_0.c1628 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2); in dce_v10_0_afmt_setmode()
1706 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2); in dce_v10_0_afmt_setmode()
H A Ddce_v11_0.c1670 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2); in dce_v11_0_afmt_setmode()
1748 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2); in dce_v11_0_afmt_setmode()