/dragonfly/sys/dev/drm/i915/ |
H A D | i915_suspend.c | 35 if (INTEL_GEN(dev_priv) <= 4) in i915_save_display() 39 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv)) in i915_save_display() 46 if (INTEL_GEN(dev_priv) <= 4) in i915_restore_display() 53 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv)) in i915_restore_display() 73 if (INTEL_GEN(dev_priv) < 7) in i915_save_state() 117 if (INTEL_GEN(dev_priv) < 7) in i915_restore_state()
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H A D | intel_ringbuffer.c | 390 if (INTEL_GEN(dev_priv) >= 4) in ring_setup_phys_status_page() 431 if (INTEL_GEN(dev_priv) >= 6) in intel_ring_setup_status_page() 465 if (INTEL_GEN(dev_priv) > 2) { in stop_ring() 568 if (INTEL_GEN(dev_priv) > 2) in init_ring_common() 1751 if (INTEL_GEN(req->i915) >= 8) in gen6_bsd_ring_flush() 1860 if (INTEL_GEN(req->i915) >= 8) in gen6_ring_flush() 2072 if (INTEL_GEN(dev_priv) >= 8) in intel_ring_default_vfuncs() 2115 if (INTEL_GEN(dev_priv) < 4) in intel_init_render_ring_buffer() 2156 if (INTEL_GEN(dev_priv) < 8) in intel_init_bsd_ring_buffer() 2177 if (INTEL_GEN(dev_priv) < 8) in intel_init_blt_ring_buffer() [all …]
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H A D | intel_fbc.c | 51 return IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8; in fbc_on_pipe_a_only() 56 return INTEL_GEN(dev_priv) < 4; in fbc_on_plane_a_only() 61 return INTEL_GEN(dev_priv) <= 3; in no_fbc_on_multiple_pipes() 97 if (INTEL_GEN(dev_priv) == 7) in intel_fbc_calculate_cfb_size() 99 else if (INTEL_GEN(dev_priv) >= 8) in intel_fbc_calculate_cfb_size() 360 if (INTEL_GEN(dev_priv) >= 5) in intel_fbc_hw_is_active() 374 if (INTEL_GEN(dev_priv) >= 7) in intel_fbc_hw_activate() 376 else if (INTEL_GEN(dev_priv) >= 5) in intel_fbc_hw_activate() 390 if (INTEL_GEN(dev_priv) >= 5) in intel_fbc_hw_deactivate() 569 if (ret && INTEL_GEN(dev_priv) <= 4) { in find_compression_threshold() [all …]
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H A D | intel_hangcheck.c | 30 if (INTEL_GEN(engine->i915) >= 8) { in ipehr_is_semaphore_wait() 47 if (INTEL_GEN(dev_priv) >= 8) { in semaphore_wait_to_signaller_ring() 115 backwards = (INTEL_GEN(dev_priv) >= 8) ? 5 : 4; in semaphore_waits_for() 138 if (INTEL_GEN(dev_priv) >= 8) { in semaphore_waits_for() 276 if (INTEL_GEN(dev_priv) >= 6 && tmp & RING_WAIT_SEMAPHORE) { in engine_stuck()
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H A D | i915_gem_tiling.c | 83 if (INTEL_GEN(i915) >= 4) { in i915_gem_fence_size() 123 if (INTEL_GEN(i915) >= 4) in i915_gem_fence_alignment() 151 if (INTEL_GEN(i915) >= 7) { in i915_tiling_ok() 154 } else if (INTEL_GEN(i915) >= 4) { in i915_tiling_ok()
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H A D | i915_irq.c | 582 if (INTEL_GEN(dev_priv) < 5) in i915_pipestat_enable_mask() 673 if (INTEL_GEN(dev_priv) >= 4) in i915_enable_asle_pipestat() 1710 if (INTEL_GEN(dev_priv) >= 3) in i9xx_pipe_crc_irq_handler() 1744 if (INTEL_GEN(dev_priv) >= 8) in gen6_rps_irq_handler() 2488 if (INTEL_GEN(dev_priv) >= 6) in ironlake_irq_handler() 2498 if (INTEL_GEN(dev_priv) >= 7) in ironlake_irq_handler() 2636 if (INTEL_GEN(dev_priv) >= 9) in gen8_de_irq_handler() 2806 if (INTEL_GEN(dev_priv) < 4) in i915_clear_error_registers() 3050 if (INTEL_GEN(dev_priv) >= 6) in gen5_gt_irq_reset() 4049 if (INTEL_GEN(dev_priv) <= 7) in intel_irq_init() [all …]
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H A D | intel_device_info.c | 350 if (INTEL_GEN(dev_priv) >= 9) { in intel_device_info_runtime_init() 374 } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) { in intel_device_info_runtime_init() 445 else if (INTEL_GEN(dev_priv) == 9) in intel_device_info_runtime_init() 447 else if (INTEL_GEN(dev_priv) >= 10) in intel_device_info_runtime_init()
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H A D | intel_engine_cs.c | 153 switch (INTEL_GEN(dev_priv)) { in __intel_engine_context_size() 155 MISSING_CASE(INTEL_GEN(dev_priv)); in __intel_engine_context_size() 189 if (INTEL_GEN(dev_priv) < 8) in __intel_engine_context_size() 692 if (INTEL_GEN(dev_priv) >= 8) in intel_engine_get_active_head() 695 else if (INTEL_GEN(dev_priv) >= 4) in intel_engine_get_active_head() 708 if (INTEL_GEN(dev_priv) >= 8) in intel_engine_get_last_batch_head() 777 switch (INTEL_GEN(dev_priv)) { in intel_engine_get_instdone() 1521 if (INTEL_GEN(dev_priv) > 2 && !(I915_READ_MODE(engine) & MODE_IDLE)) in ring_is_idle() 1617 switch (INTEL_GEN(engine->i915)) { in intel_engine_can_store_dword() 1759 } else if (INTEL_GEN(dev_priv) > 6) { in intel_engine_dump()
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H A D | intel_sprite.c | 898 if (INTEL_GEN(dev_priv) >= 9) { in intel_check_sprite_plane() 1014 if (INTEL_GEN(dev_priv) < 9 && (src_w > 2048 || src_h > 2048 || in intel_check_sprite_plane() 1033 if (INTEL_GEN(dev_priv) >= 9) { in intel_check_sprite_plane() 1045 } else if (INTEL_GEN(dev_priv) >= 7) { in intel_check_sprite_plane() 1260 if (INTEL_GEN(dev_priv) >= 9) in intel_sprite_plane_format_mod_supported() 1307 if (INTEL_GEN(dev_priv) >= 10) { in intel_sprite_plane_create() 1318 } else if (INTEL_GEN(dev_priv) >= 9) { in intel_sprite_plane_create() 1340 } else if (INTEL_GEN(dev_priv) >= 7) { in intel_sprite_plane_create() 1374 if (INTEL_GEN(dev_priv) >= 9) { in intel_sprite_plane_create() 1395 if (INTEL_GEN(dev_priv) >= 9) in intel_sprite_plane_create()
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H A D | intel_display.c | 1064 if (INTEL_GEN(dev_priv) >= 4) { in intel_wait_for_pipe_off() 2089 if (INTEL_GEN(dev_priv) >= 9) in intel_surf_alignment() 3164 if (INTEL_GEN(dev_priv) < 4) in i9xx_plane_ctl() 3217 if (INTEL_GEN(dev_priv) >= 4) in i9xx_check_plane_surface() 3261 if (INTEL_GEN(dev_priv) >= 4) in i9xx_update_primary_plane() 5414 if (INTEL_GEN(dev_priv) >= 9) in haswell_crtc_enable() 5560 if (INTEL_GEN(dev_priv) >= 9) in haswell_crtc_disable() 6880 if (INTEL_GEN(dev_priv) >= 4) in i9xx_compute_dpll() 6967 if (INTEL_GEN(dev_priv) > 3) in intel_set_pipe_timings() 7529 if (INTEL_GEN(dev_priv) < 4) in i9xx_get_pipe_config() [all …]
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H A D | i915_gem_context.c | 607 (i915_modparams.semaphores && INTEL_GEN(dev_priv) == 7) ? in mi_set_context() 614 if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8) in mi_set_context() 621 if (INTEL_GEN(dev_priv) >= 7) in mi_set_context() 629 if (INTEL_GEN(dev_priv) >= 7) { in mi_set_context() 656 if (INTEL_GEN(dev_priv) >= 7) { in mi_set_context() 750 if (INTEL_GEN(engine->i915) < 8) in needs_pd_load_pre()
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H A D | i915_gem_stolen.c | 124 if (INTEL_GEN(dev_priv) >= 3) { in i915_stolen_to_dma() 219 if (INTEL_GEN(dev_priv) <= 4 && in i915_stolen_to_dma() 441 if (intel_vtd_active() && INTEL_GEN(dev_priv) < 8) { in i915_gem_init_stolen() 518 if (INTEL_GEN(dev_priv) >= 8) in i915_gem_init_stolen()
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H A D | intel_pm.c | 2552 if (INTEL_GEN(dev_priv) >= 8) in ilk_display_fifo_size() 2564 if (INTEL_GEN(dev_priv) >= 8) in ilk_plane_wm_reg_max() 2581 if (INTEL_GEN(dev_priv) >= 7) in ilk_cursor_wm_reg_max() 2589 if (INTEL_GEN(dev_priv) >= 8) in ilk_fbc_wm_reg_max() 2618 if (INTEL_GEN(dev_priv) <= 6) in ilk_plane_wm_max() 2906 if (INTEL_GEN(dev_priv) >= 9) in ilk_wm_max_level() 2935 if (INTEL_GEN(dev_priv) >= 9) in intel_print_wm_latency() 4640 if (INTEL_GEN(dev_priv) <= 9) in skl_compute_transition_wm() 7977 if (INTEL_GEN(dev_priv) < 6) in intel_suspend_gt_powersave() 9220 if (INTEL_GEN(dev_priv) > 6) in sandybridge_pcode_read() [all …]
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H A D | intel_uncore.c | 319 if (INTEL_GEN(dev_priv) < 9) in intel_uncore_edram_size() 329 INTEL_GEN(dev_priv) >= 9) { in intel_uncore_edram_detect() 720 (INTEL_GEN(dev_priv) >= 9 || \ 1136 if (INTEL_GEN(dev_priv) <= 5 || intel_vgpu_active(dev_priv)) in intel_uncore_fw_domains_init() 1150 if (INTEL_GEN(dev_priv) >= 9) { in intel_uncore_fw_domains_init() 1419 if (INTEL_GEN(dev_priv) < 3) in i915_stop_engines() 1862 } else if (INTEL_GEN(dev_priv) >= 6) { in intel_uncore_forcewake_for_read()
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H A D | intel_lvds.c | 141 if (INTEL_GEN(dev_priv) < 5) in intel_lvds_get_config() 146 if (INTEL_GEN(dev_priv) < 4) { in intel_lvds_get_config() 398 if (INTEL_GEN(dev_priv) < 4 && intel_crtc->pipe == 0) { in intel_lvds_compute_config() 920 if (INTEL_GEN(dev_priv) <= 4 && in intel_lvds_supported()
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H A D | intel_lrc.c | 240 if (INTEL_GEN(dev_priv) >= 9) in intel_sanitize_enable_execlists() 1394 switch (INTEL_GEN(engine->i915)) { in intel_init_workaround_bb() 1406 MISSING_CASE(INTEL_GEN(engine->i915)); in intel_init_workaround_bb() 2000 if (INTEL_GEN(dev_priv) >= 9) in logical_render_ring_init() 2043 if (INTEL_GEN(dev_priv) < 9) in make_rpcs() 2081 switch (INTEL_GEN(engine->i915)) { in intel_lr_indirect_ctx_offset() 2083 MISSING_CASE(INTEL_GEN(engine->i915)); in intel_lr_indirect_ctx_offset()
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H A D | i915_drv.c | 460 int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; in intel_alloc_mchbar_resource() 465 if (INTEL_GEN(dev_priv) >= 4) in intel_alloc_mchbar_resource() 489 if (INTEL_GEN(dev_priv) >= 4) in intel_alloc_mchbar_resource() 502 int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; in intel_setup_mchbar() 541 int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; in intel_teardown_mchbar() 1024 if (INTEL_GEN(dev_priv) < 5) in i915_mmio_setup() 1236 if (INTEL_GEN(dev_priv) >= 5) { in i915_driver_init_hw() 1708 if (!(hibernation && INTEL_GEN(dev_priv) < 6))
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H A D | i915_gem_gtt.c | 157 if (enable_ppgtt == 0 && INTEL_GEN(dev_priv) < 9) in intel_sanitize_enable_ppgtt() 2144 INTEL_GEN(dev_priv) <= 10) in gtt_write_workarounds() 2167 else if (INTEL_GEN(dev_priv) >= 8) in i915_ppgtt_init_hw() 2170 MISSING_CASE(INTEL_GEN(dev_priv)); in i915_ppgtt_init_hw() 2289 if (INTEL_GEN(dev_priv) < 6) in i915_gem_suspend_gtt_mappings() 3287 if (INTEL_GEN(dev_priv) >= 10) in setup_private_pat() 3325 if (INTEL_GEN(dev_priv) >= 9) { in gen8_gmch_probe() 3420 else if (INTEL_GEN(dev_priv) >= 7) in gen6_gmch_probe() 3481 if (INTEL_GEN(dev_priv) <= 5) in i915_ggtt_probe_hw() 3483 else if (INTEL_GEN(dev_priv) < 8) in i915_ggtt_probe_hw() [all …]
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H A D | intel_crt.c | 155 if (INTEL_GEN(dev_priv) >= 5) in intel_crt_set_dpms() 809 else if (INTEL_GEN(dev_priv) < 4) in intel_crt_detect() 864 if (INTEL_GEN(dev_priv) >= 5) { in intel_crt_reset()
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H A D | i915_gem_fence_reg.c | 556 if (INTEL_GEN(dev_priv) >= 8 || IS_VALLEYVIEW(dev_priv)) { in i915_gem_detect_bit_6_swizzle() 566 } else if (INTEL_GEN(dev_priv) >= 6) { in i915_gem_detect_bit_6_swizzle()
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H A D | intel_ringbuffer.h | 96 (INTEL_GEN(dev_priv__) == 7 ? \ 100 (INTEL_GEN(dev_priv__) == 7 ? \
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H A D | intel_atomic_plane.c | 184 if (state->fb && INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable && in intel_plane_atomic_check_with_state()
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H A D | i915_sysfs.c | 256 if (INTEL_GEN(dev_priv) >= 9) 605 else if (INTEL_GEN(dev_priv) >= 6) in i915_setup_sysfs()
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H A D | i915_gem_render_state.c | 43 switch (INTEL_GEN(engine->i915)) { in render_state_get_rodata()
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H A D | intel_sdvo.c | 1340 if (INTEL_GEN(dev_priv) >= 4) { in intel_sdvo_pre_enable() 1346 if (INTEL_GEN(dev_priv) < 5) in intel_sdvo_pre_enable() 1363 WARN_ON_ONCE(INTEL_GEN(dev_priv) < 4); in intel_sdvo_pre_enable() 1367 if (INTEL_GEN(dev_priv) >= 4) { in intel_sdvo_pre_enable() 1378 INTEL_GEN(dev_priv) < 5) in intel_sdvo_pre_enable() 2439 if (INTEL_GEN(dev_priv) >= 4 && IS_MOBILE(dev_priv)) { in intel_sdvo_add_hdmi_properties() 2508 if (INTEL_GEN(dev_priv) >= 4 && in intel_sdvo_dvi_init()
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