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Searched refs:LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h7637 #define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK 0xffff0000L macro
H A Ddce_8_0_sh_mask.h3215 #define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK 0xffff0000 macro
H A Ddce_10_0_sh_mask.h3137 #define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK 0xffff0000 macro
H A Ddce_11_0_sh_mask.h3207 #define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK 0xffff0000 macro
H A Ddce_11_2_sh_mask.h3455 #define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK 0xffff0000 macro
H A Ddce_12_0_sh_mask.h9286 #define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_sh_mask.h40035 #define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK … macro