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Searched refs:MC_SEQ_MISC0 (Results 1 – 12 of 12) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
H A Dbtcd.h119 #define MC_SEQ_MISC0 0x2a00 macro
H A Dnid.h209 #define MC_SEQ_MISC0 0x2a00 macro
790 #define MC_SEQ_MISC0 0x2a00 macro
H A Drv770d.h285 #define MC_SEQ_MISC0 0x2a00 macro
H A Dsid.h551 #define MC_SEQ_MISC0 0x2a00 macro
H A Dcikd.h676 #define MC_SEQ_MISC0 0x2a00 macro
H A Drv770_dpm.c736 tmp = RREG32(MC_SEQ_MISC0) & 3; in rv770_calculate_memory_refresh_rate()
1599 tmp = RREG32(MC_SEQ_MISC0); in rv770_get_memory_type()
H A Dni.c649 mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT; in ni_mc_load_microcode()
H A Dci_dpm.c2537 tmp = RREG32(MC_SEQ_MISC0); in ci_register_patching_mc_arb()
4572 tmp = RREG32(MC_SEQ_MISC0); in ci_register_patching_mc_seq()
5127 tmp = RREG32(MC_SEQ_MISC0); in ci_get_memory_type()
H A Dsi.c1766 if (((RREG32(MC_SEQ_MISC0) & 0xff000000) >> 24) == 0x58) in si_init_microcode()
5828 tmp = RREG32(MC_SEQ_MISC0); in si_lbpw_supported()
H A Dsi_dpm.c3209 tmp = RREG32(MC_SEQ_MISC0); in si_is_special_1gb_platform()
4285 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3); in si_calculate_memory_refresh_rate()
H A Dcik.c1918 tmp = RREG32(MC_SEQ_MISC0); in ci_mc_load_microcode()
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dsi_dpm.c3668 tmp = RREG32(MC_SEQ_MISC0); in si_is_special_1gb_platform()
4750 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3); in si_calculate_memory_refresh_rate()